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| TMP1962C10BXBG 32-Bit RISC Microprocessor TX19 Family TMP1962C10BXBG 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16TM Application-Specific Extensions (ASE) for improved code density. The TMP1962 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1962 is suitable for low-voltage, low-power applications. Features of the TMP1962 include the following: (1) TX19 core processor 1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed * * 2) * * * * The 16-bit ISA is object-code compatible with the code-efficient MIPS16TM ASE. The 32-bit ISA is object-code compatible with the high-performance TX39 family. Combines high performance with low power consumption. High performance Single clock cycle execution for most instructions 3-operand computational instructions for high instruction throughput 5-stage pipeline 030619EBP * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. TMP1962-1 2006-02-21 TMP1962C10BXBG * * * * * 3) On-chip high-speed memory DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. Low power consumption Optimized design using a low-power cell library Programmable standby modes in which processor clocks are stopped Fast interrupt response suitable for real-time control * * * Distinct starting locations for each interrupt service routine Automatically generated vectors for each interrupt source Automatic updates of the interrupt mask level (2) On-chip program memory and data memory Product TMP1962C10AXB TMP1962F10AXB On-Chip ROM 1 Mbyte 1 Mbyte (Flash) On-Chip RAM 40 Kbyte 40 Kbyte * ROM correction logic (8 words x 8 blocks) (3) External memory expansion * * 16-Mbyte off-chip address space for code and data External data bus Separate bus/multiplexed bus: Dynamic bus sizing for 8-bit and 16-bit data ports (4) 8-channel DMA controller * * Interrupt- or software-triggered Transfer destination: On-chip memory, on-chip peripherals, external memory, external peripherals (5) 12-channel 8-bit timer * * * 8/16/24/32-Bit Interval Timer mode 8-Bit PWM mode 8-Bit PPG mode (6) 4-channel 16-bit timer * * * * * 16-Bit Interval Timer mode 16-Bit Event Counter mode 16-bit PPG output Input capture 2-phase pulse input counter (2 channels) TMP1962-2 2006-02-21 TMP1962C10BXBG (7) 32-bit input capture * * * 32-bit input capture registers (8 channels) 32-bit compare registers (8 channels) 32-bit time base timer (1 channel) (8) 7-channel general-purpose serial interface * Either UART mode or Synchronous mode can be selected. (9) 1-channel serial bus interface * Either I2C Bus mode or Clock-Synchronous mode can be selected. (10) 24-channel 10-bit A/D converter (with internal sample/hold) * * * * External trigger supported Fixed-Channel or Channel Scan mode Single Conversion or Continuous Conversion mode Timer monitoring (11) 1-channel watchdog timer (12) 4-channel chip select/wait controller (13) Interrupt sources * * * 4 CPU interrupts: Software interrupt instruction 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt 25 external interrupts: 7 priority levels, with the exception of the NMI interrupt The external sources include 14 KWUP sources, which are all assigned to a single interrupt vector. (14) 202-pin input/output ports (15) Standby modes * Two standby modes: IDLE, STOP (16) Clock generator * * On-chip PLL (x3) Clock gear: Divides the high-speed clock by 1/2, 1/4 or 1/8. TMP1962-3 2006-02-21 TMP1962C10BXBG (17) Optional big-endian alignment Big-endian Higher address 31 8 4 0 Lower address 24 23 9 5 1 16 15 10 6 2 87 11 7 3 0 Word address 8 4 0 * * Byte 0 is the highest-order byte (bits 31-24). The address of a word data item is the address of its highest-order byte (byte 0). Little-endian Higher address 31 11 7 3 Lower address 24 23 10 6 2 16 15 9 5 1 87 8 4 0 0 Word address 8 4 0 * * Byte 0 is the lowest-order byte (bits 7-0). The address of a word data item is the address of its lowest-order byte (byte 0). (18) Operating frequency * (19) Package * P-FBGA281 (13 mm x 13 mm, 0.65-mm pitch) 40.5 MHz (Vcc = 1.35 V to 1.65 V) TMP1962-4 2006-02-21 TMP1962C10BXBG TX19 Processor Core TX19 CPU MAC 1 Mbyte Flash ROM ROM correction DSU 40 Kbyte RAM DMAC (8ch) CG INTC EBIF I/O Bus I/F 8-bit TMRA 0/1 to A/B (12ch) 16-bit TMRB 0 to 3(4ch) PORT0 to PORT6 (Shared with external bus interface) 32-bit TMRC TBT(1ch) PORT7 to PORT9 (Shared with ADC input) 32-bit TMRC Input Capture 0 to 7 (8ch) PORTA to PORTL, PORTN (Shared with functional pins) 32-bit TMRC Compare 0 to 7 (8ch) 10-bit ADC (24ch) SIO 0 to 6 (7ch) PORTM, PORTO to PORTP (General-purpose ports) IC (1ch) 2 KWUP 0 to D (14ch) WDT Figure 1.1 TMP1962 Block Diagram TMP1962-5 2006-02-21 TMP1962C10BXBG 2. Signal Descriptions This section contains pin assignments for the TMP1962 as well as brief descriptions of the TMP1962 input and output signals. 2.1 Pin Assignment (TOP View) The following illustrates the TMP1962 pin assignment. A1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 F7 A8 B8 C8 D8 E8 F8 A9 B9 C9 D9 E9 F9 A10 A11 A12 A13 A14 A15 A16 A17 B10 B11 B12 B13 B14 B15 B16 B17 B18 C10 C11 C12 C13 C14 C15 C16 C17 C18 D10 D11 D12 D13 D14 D15 D16 D17 D18 E10 E11 E12 E13 E14 E15 E16 E17 E18 F10 F11 F12 F14 F15 F16 F17 F18 G13 G14 G15 G16 G17 G18 H13 H14 H15 H16 H17 H18 J13 J14 J15 J16 J17 J18 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 G6 H6 J6 K6 L6 M6 N7 P6 R6 T6 U6 V6 P7 R7 T7 U7 V7 N8 P8 R8 T8 U8 V8 N9 P9 R9 T9 U9 V9 N10 N11 N12 K13 K14 K15 K16 K17 K18 L13 L14 L15 L16 L17 L18 M13 M14 M15 M16 M17 M18 N14 N15 N16 N17 N18 P10 P11 P12 P13 P14 P15 P16 P17 P18 R10 R11 R12 R13 R14 R15 R16 R17 R18 T10 T11 T12 T13 T14 T15 T16 T17 T18 U10 U11 U12 U13 U14 U15 U16 U17 U18 V10 V11 V12 V13 V14 V15 V16 V17 Figure 2.1 P-FBGA281 Pin Assignment Table 2.1 shows the correspondence between the numbers and names of the TMP1962 pins. Table 2.1 Pin Numbers and Names (1/2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 NC VREFL P90/AIN16 P93/AIN19 P80/AIN8 P83/AIN11 P70/AIN0 P74/AIN4 NC Pin Name Pin No. Pin Name Pin No. B8 B9 Pin Name P75/AIN5 PL0/TA4IN Pin No. C2 C3 C4 C5 C6 C7 C8 C9 Pin Name PCST3 (DSU) P92/AIN18 P95/AIN21 P82/AIN10 P85/AIN13 P72/AIN2 AVSS PL1/TA6IN Pin No. Pin Name A13 PK1/KEY1 A14 PI1/INT1 A15 PI3/INT3 A16 PI6/INTA A17 X2 B1 B2 B3 B4 B5 B6 B7 AVCC31 VREFH P91/AIN17 P94/AIN20 P81/AIN9 P84/AIN12 P71/AIN1 C14 PK6/KEY6 C15 PI5/INT9 C16 TCK (JTAG) C17 CVCC15 (CVCC2) C18 NC (XT2) D1 D2 D3 D4 D5 D6 D7 SDAO/TPC (DSU) PCST2 (DSU) SDI/ DINT (DSU) DVCC15 (DVCC22) P96/AIN22 P86/AIN14 P73/AIN3 B10 PL3/TAAIN B11 PM1 B12 PM4 B13 PK2/KEY2 B14 PI2/INT2 B15 PI4/INT4 B16 PI7 B17 CVSS B18 X1 C1 PCST0 (DSU) C10 PL4/TB0IN0 C11 PM2 C12 PM5 C13 PK3/KEY3 A10 PL2/TA8IN A11 PM0 A12 PK0/KEY0 TMP1962-6 2006-02-21 TMP1962C10BXBG Table 2.1 Pin Numbers and Names (2/2) Pin No. D8 D9 Pin Name Pin No. G1 G2 G3 G4 G5 G6 G13 Pin Name Pin No. Pin Name Pin No. P1 P2 P3 P4 P5 P6 P7 P8 P9 Pin Name Pin No. T8 T9 Pin Name PD4/TXD4 PC0/TXD0 DVCC15 (DVCC22) F18 P44/SCOUT DVSS RESET K14 P12/D10/AD10 K15 P13/D11/AD11 K16 P14/D12/AD12 K17 DVCC33 K18 P15/D13/AD13 L1 L2 L3 L4 L5 L6 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 NC (FVCC3) PO1 PO2 PO3 PO4 PO7 NC (TEST3) P06/D6/AD6 NC (FVCC2) P07/D7/AD7 P10/D8/AD8 P11/D9/AD9 PO0 PP5 PP6 PP7 PB7/TB3OUT DVCC32 N18 DVSS PP0 PB2/TB2IN0/INT5 PB3/TB2IN1/INT6 PB4/TB2OUT PB5/TB3IN0/INT7 PG5/TC5IN PG7/TC7IN PD6/SCLK4/ CTS4 PC2/SCLK0/ CTS0 D10 PL5/TB0IN1 D11 PM3 D12 PM6 D13 PK4/KEY4 D14 PK7/KEY7 D15 DVCC34 D16 TDI (JTAG) D17 TDO (JTAG) D18 NC (XT1) E1 E2 E3 E4 E5 E6 E7 E8 E9 DCLK (DSU) PCST1 (DSU) DBGE TEST5 DVCC2 (FVCC2) NC (FVSS) PJ0/INT0 BW0 TRST T10 PC3/TXD1 T11 PH4/TCOUT4 T12 PE2/SCLK5/ CTS5 T13 PE5/KEYB T14 P53/A3 T15 P56/A6 T16 P62/A10 T17 P65/A13 T18 P20/A16/A0 U1 U2 U3 U4 U5 U6 U7 U8 U9 PA0/TA0IN PA3/TA3OUT PA6/TA9OUT PF1/SI/SCL PF5/ DREQ3 PG2/TC2IN PD2/RXD3 DVCC32 PC7/RXD2 G14 NC (CAP1) G15 P41/ CS1 G16 P37/ALE G17 P35/ BUSAK G18 NC (FVCC2) H1 H2 H3 H4 H5 H6 NMI P10 PC5/SCLK1/ CTS1 P11 PH6/TCOUT6 P12 NC P13 P50/A0 P14 P51/A1 P15 P54/A4 P16 P23/A19/A3 P17 P24/A20/A4 P18 P25/A21/A5 R1 R2 R3 R4 R5 R6 R7 R8 R9 PB0/TB0OUT PB1/TB1OUT PF3/ DREQ2 PF4/ DACK2 PF7/TBTIN PG4/TC4IN PG6/TC6IN PD5/RXD4 PC1/RXD0 PJ3/INTLV PJ4/ENDIAN P97/AIN23 P87/AIN15 P76/AIN6 P77/AIN7 DVCC31 PN7 BW1 PLLOFF NC (TEST1) H13 NC (TEST2) H14 P31/ WR H15 P32/ HWR H16 P33/WAIT/RDY H17 P30/ RD H18 P40/ CS0 J1 J2 J3 J4 J5 J6 J13 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K6 PN2/SCLK6/ CTS6 PN3 PN4 PN5 PN6 DVCC15 (DVCC22) NC (FVSS) P16/D14/AD14 DVSS P17/D15/AD15 P36/ R / W P34/ BUSRQ PN0/TXD6 PN1/RXD6 PO5 PO6 NC (FVSS) DVSS E10 PL6/TB1IN0 E11 PL7/TB1IN1 E12 PM7 E13 PK5/KEY5 E14 NC E15 TMS (JTAG) E16 NC (CVCCH) E17 NC E18 DVCC15 (DVCC22) F1 F2 F3 F4 F5 F7 F8 F9 DVSS DRESET U10 PH1/TCOUT1 U11 PH3/TCOUT3 U12 PE1/RXD5 U13 PE4/KEYA U14 DVCC32 U15 P57/A7 U16 P63/A11 U17 P66/A14 U18 DVCC33 V2 V3 V4 V5 V6 V7 V8 V9 PA2/TA2IN PA5/TA7OUT PF0/SO/SDA PG0/TC0IN PG1/TC1IN PD1/TXD3 PD0/SCLK2/ CTS2 PC6/TXD2 M13 NC (TEST4) M14 P02/D2/AD2 M15 NC (FVSS) M16 P03/D3/AD3 M17 P04/D4/AD4 M18 P05/D5/AD5 N1 N2 N3 N4 N5 N7 N8 N9 PP1 PP2 PP3 PP4 PB6/TB3IN1/INT8 DVSS PD7/KEY8 R10 PC4/RXD1 R11 PH5/TCOUT5 R12 PH7/TCOUT7 R13 PE6/KEYC R14 P52/A2 R15 P55/A5 R16 P61/A9 R17 P21/A17/A1 T1 T2 T3 T4 T5 T6 T7 PA1/TA1OUT PA4/TA5OUT PA7/TABOUT PF2/SCK PF6/ DACK3 PG3/TC3IN PD3/SCLK3/ CTS3 SYSRDY PJ1/BUSMD PJ2/ BOOT AVSS AVSS AVCC32 DVCC15 (DVCC22) R18 P22/A18/A2 F10 DVCC34 F11 PI0/ ADTRG F12 DVSS F14 NC (CAP2) F15 P42/ CS2 F16 P43/ CS3 F17 DVCC33 N10 DVSS N11 RSTPUP N12 DVSS N14 P26/A22/A6 N15 P27/A23/A7 N16 P00/D0/AD0 N17 P01/D1/AD1 V10 PH0/TCOUT0 V11 PH2/TCOUT2 V12 PE0/TXD5 V13 PE3/KEY9 V14 PE7/KEYD V15 P60/A8 V16 P64/A12 V17 P67/A15 K13 NC (TEST0) Note : Parentheses indicate the pin name on TMP1962F10AXBG with on-chip flash memory. (Except "DSU" and "JTAG". The same pin names are used for the on-chip mask ROM type and on-chip flash memory type.) TMP1962-7 2006-02-21 TMP1962C10BXBG 2.2 Pin Usage Information Table 2.2 lists the input and output pins of the TMP1962, including alternate pin names and functions for multi-function pins. Table 2.2 Pin Names and Functions (1/6) Pin Name P00 - P07 D0 - D7 AD0 - D7 P10 - P17 D8 - D15 AD8 - AD15 A8 - A15 P20 - P27 A16 - A23 A0 - A7 A16 - A23 P30 RD Number of Pins 8 Type Input/Output Input/Output Input/Output Function Port 0: Individually programmable as input or output Data (Lower): Bits 0 to 7 of the data bus (Separate Bus mode) Address/Data (Lower): Bits 0 to 7 of the address/data bus (Multiplexed Bus mode) Port 1: Individually programmable as input or output Data (Upper): Bits 8 to 15 of the data bus (Separate Bus mode) Address/Data (Upper): Bits 8 to 15 of the address/data bus (Multiplexed Bus mode) Address: Bits 8 to 15 of the address bus (Multiplexed Bus mode) Port 2: Individually programmable as input or output Address: Bits 16 to 23 of the address bus (Separate Bus mode) Address: Bits 0 to 7 of the address bus (Multiplexed Bus mode) Address: Bits 16 to 23 of the address bus (Multiplexed Bus mode) Port 30: Output-only Read Strobe: Asserted during a read operation from an external memory device Port 31: Output-only Write Strobe: Asserted during a write operation on D0 to D7 Port 32: Programmable as input or output (with internal pull-up resistor) Higher Write Strobe: Asserted during a write operation on D8 to D15 Port 33: Programmable as input or output (with internal pull-up resistor) Wait: Causes the CPU to suspend external bus activity Ready: Notifies the CPU that the bus is ready Port 34: Programmable as input or output (with internal pull-up resistor) Bus Request: Asserted by an external bus master to request bus mastership Port 35: Programmable as input or output (with internal pull-up resistor) Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to BUSRQ 8 Input/Output Input/Output Input/Output Output 8 Input/Output Output Output Output 1 1 1 1 Output Output Output Output Input/Output Output Input/Output Input Input P31 WR P32 HWR P33 WAIT RDY P34 BUSRQ 1 1 Input/Output Input Input/Output Output P35 BUSAK P36 R/ W 1 Input/Output Output Port 36: Programmable as input or output (with internal pull-up resistor) Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle Port 37: Programmable as input or output Address Latch Enable (enabled only when an external memory device is accessed) Port 40: Programmable as input or output (with internal pull-up resistor) Chip Select 0: Asserted low to enable external devices at programmed addresses Port 41: Programmable as input or output (with internal pull-up resistor) Chip Select 1: Asserted low to enable external devices at programmed addresses Port 42: Programmable as input or output (with internal pull-up resistor) Chip Select 2: Asserted low to enable external devices at programmed addresses Port 43: Programmable as input or output (with internal pull-up resistor) Chip Select 3: Asserted low to enable external devices at programmed addresses Port 44: Programmable as input or output System Clock Output: Drives out a clock signal at the same frequency as the CPU clock (high-speed or low-speed) or half the high-speed clock frequency Port 5: Individually programmable as input or output Address: Bits 0 to 7 of the address bus (Separate Bus mode) Port 6: Individually programmable as input or output Address: Bits 8 to 15 of the address bus (Separate Bus mode) P37 ALE P40 CS0 1 1 1 1 1 1 Input/Output Output Input/Output Output Input/Output Output Input/Output Output Input/Output Output Input/Output Output P41 CS1 P42 CS2 P43 CS3 P44 SCOUT P50 - P57 A0 - A7 P60 - P67 A8 - A15 8 8 Input/Output Output Input/Output Output TMP1962-8 2006-02-21 TMP1962C10BXBG Table 2.2 Pin Names and Functions (2/6) Pin Name P70 - P77 AN0 - AN7 P80 - P87 AN8 - AN15 P90 - P97 AN16 - AN23 PI0 ADTRG Number of Pins 8 8 8 1 Type Input Input Input Input Input Input Input/Output Input Port 7: Input-only Function Analog Input: Input to the on-chip A/D converter Port 8: Input-only Analog Input: Input to the on-chip A/D converter Port 9: Input-only Analog Input: Input to the on-chip A/D converter Port I0: Programmable as input or output A/D Trigger: Starts an A/D conversion Schmitt-triggered input Port I1: Programmable as input or output Interrupt Request 1: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I2: Programmable as input or output Interrupt Request 2: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I3: Programmable as input or output Interrupt Request 3: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I4: Programmable as input or output Interrupt Request 4: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I5: Programmable as input or output Interrupt Request 9: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I6: Programmable as input or output Interrupt Request A: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input Port I7: Programmable as input or output Port A0: Programmable as input or output 8-Bit Timer 0 Input: Input to 8-bit timer 0 Port A1: Programmable as input or output 8-Bit Timer 01 Output: Output from either 8-bit timer 0 or 1 Port A2: Programmable as input or output 8-Bit Timer 2 Input: Input to 8-bit timer 2 Port A3: Programmable as input or output 8-Bit Timer 23 Output: Output from either 8-bit timer 2 or 3 Port A4: Programmable as input or output 8-Bit Timer 45 Output: Output from either 8-bit timer 4 or 5 Port A5: Programmable as input or output 8-Bit Timer 67 Output: Output from either 8-bit timer 6 or 7 Port A6: Programmable as input or output 8-Bit Timer 89 Output: Output from either 8-bit timer 8 or 9 Port A7: Programmable as input or output 8-Bit Timer AB Output: Output from either 8-bit timer A or B Port B0: Programmable as input or output 16-Bit Timer 0 Output: Output from 16-bit timer 0 Port B1: Programmable as input or output 16-Bit Timer 1 Output: Output from 16-bit timer 1 PI1 INT1 1 Input/Output Input PI2 INT2 1 Input/Output Input PI3 INT3 1 Input/Output Input PI4 INT4 1 Input/Output Input PI5 INT9 1 Input/Output Input PI6 INTA 1 Input/Output Input PI7 PA0 TA0IN PA1 TA1OUT PA2 TA2IN PA3 TA3OUT PA4 TA5OUT PA5 TA7OUT PA6 TA9OUT PA7 TABOUT PB0 TB0OUT PB1 TB1OUT 1 1 1 1 1 1 1 1 1 1 1 Input/Output Input/Output Input Input/Output Output Input/Output Input Input/Output Output Input/Output Output Input/Output Output Input/Output Input Input/Output Output Input/Output Output Input/Output Output TMP1962-9 2006-02-21 TMP1962C10BXBG Table 2.2 Pin Names and Functions (3/6) Pin Name PB2 TB2IN0 INT5 PB3 TB2IN1 INT6 PB4 TB2OUT PB5 TB3IN0 INT7 PB6 TB3IN1 INT8 PB7 TB3OUT PC0 TXD0 PC1 RXD0 PC2 SCLK0 CTS0 Number of Pins 1 Type Input/Output Input Input Input/Output Input Input Output Output Output Input Input Output Input Input Output Output Input/Output Output Input/Output Input Input/Output Input Input Input/Output Output Input/Output Input Input/Output Input Input Input/Output Output Input/Output Input Input/Output Input Input Input/Output Output Input/Output Input Input/Output Input Input Input/Output Output Input/Output Input Input/Output Input Input Input/Output Input Function Port B2: Programmable as input or output 16-Bit Timer 2 Input 0: Count/capture trigger input to 16-bit timer 2 Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B3: Programmable as input or output 16-Bit Timer 2 Input 1: Capture trigger input to 16-bit timer 2 Interrupt Request 6: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B4: Programmable as input or output 16-Bit Timer 2 Output: Output from 16-bit timer 2 Port B5: Programmable as input or output 16-Bit Timer 3 Input 0: Count/capture trigger input to 16-bit timer 3 Interrupt Request 7: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B6: Programmable as input or output 16-Bit Timer 3 Input 1: Capture trigger input to 16-bit timer 3 Interrupt Request 8: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B7: Programmable as input or output 16-Bit Timer 3 Output: Output from 16-bit timer 3 Port C0: Programmable as input or output Serial Transmit Data 0: Programmable as a push-pull or open-drain output Port C1: Programmable as input or output Serial Receive Data 0 Port C2: Programmable as input or output Serial Clock Input/Output 0 Serial Clear-to-Send 0: Programmable as a push-pull or open-drain output Port C3: Programmable as input or output Serial Transmit Data 1: Programmable as a push-pull or open-drain output Port C4: Programmable as input or output Serial Receive Data 1 Port C5: Programmable as input or output Serial Clock Input/Output 1 Serial Clear-to-Send 1: Programmable as a push-pull or open-drain output Port C6: Programmable as input or output Serial Transmit Data 2: Programmable as a push-pull or open-drain output Port C7: Programmable as input or output Serial Receive Data 2 Port D0: Programmable as input or output Serial Clock Input/Output 2 Serial Clear-to-Send 2: Programmable as a push-pull or open-drain output Port D1: Programmable as input or output Serial Transmit Data 3: Programmable as a push-pull or open-drain output Port D2: Programmable as input or output Serial Receive Data 3 Port D3: Programmable as input or output Serial Clock Input/Output 3 Serial Clear-to-Send 3: Programmable as a push-pull or open-drain output Port D4: Programmable as input or output Serial Transmit Data 4: Programmable as a push-pull or open-drain output Port D5: Programmable as input or output Serial Receive Data 4 Port D6: Programmable as input or output Serial Clock Input/Output 4 Serial Clear-to-Send 4: Programmable as a push-pull or open-drain output Port D7: Programmable as input or output Key-Pressed Wake-up Input 8 (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input 1 1 1 1 1 1 1 1 PC3 TXD1 PC4 RXD1 PC5 SCLK1 CTS1 1 1 1 PC6 TXD2 PC7 RXD2 PD0 SCLK2 CTS2 1 1 1 PD1 TXD3 PD2 RXD3 PD3 SCLK3 CTS3 1 1 1 PD4 TXD4 PD5 RXD4 PD6 SCLK4 CTS4 1 1 1 PD7 KEY8 1 TMP1962-10 2006-02-21 TMP1962C10BXBG Table 2.2 Pin Names and Functions (4/6) Pin Name PE0 TXD5 PE1 RXD5 PE2 SCLK5 CTS5 Number of Pins 1 1 1 Type Input/Output Output Input/Output Input Input/Output Input Input Input/Output Input Function Port E0: Programmable as input or output Serial Transmit Data 5: Programmable as a push-pull or open-drain output Port E1: Programmable as input or output Serial Receive Data 5 Port E2: Programmable as input or output Serial Clock Input/Output 5 Serial Clear-to-Send 5: Programmable as a push-pull or open-drain output Port E3: Programmable as input or output Key-Pressed Wake-up Input 9 (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port E4: Programmable as input or output Key-Pressed Wake-up Input A (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port E5: Programmable as input or output Key-Pressed Wake-up Input B (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port E6: Programmable as input or output Key-Pressed Wake-up Input C (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port E7: Programmable as input or output Key-Pressed Wake-up Input D (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port F0: Programmable as input or output Data transmit pin when the Serial Bus Interface is in SIO mode Data transmit/receive pin when the Serial Bus Interface is in I2C mode Programmable as a push-pull or open-drain output Schmitt-triggered input Port F1: Programmable as input or output Data receive pin when the Serial Bus Interface is in SIO mode Clock input/output pin when the Serial Bus Interface is in I2C mode Programmable as a push-pull or open-drain output Schmitt-triggered input Port F2: Programmable as input or output Clock input/output pin when the Serial Bus Interface is in SIO mode Port F3: Programmable as input or output DMA Request 2: Asserted by an external input/output device to request DMA transfer with DMAC2 Port F4: Programmable as input or output DMA Acknowledge 2: Indicates acknowledgement for a DMA transfer request made with DREQ2 Port F5: Programmable as input or output DMA Request 3: Asserted by an external input/output device to request DMA transfer with DMAC3 Port F6: Programmable as input or output DMA Acknowledge 3: Indicates acknowledgement for a DMA transfer request made with DREQ3 Port F7: Programmable as input or output 32-Bit Time Base Timer Input: Count input to the 32-bit time base timer Port G: Individually programmable as input or output 32-Bit Timer Capture Trigger Input Port H: Individually programmable as input or output 32-Bit Timer Compare Match Output Port J0: Programmable as input or output Interrupt Request 0: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt-triggered input PE3 KEY9 1 PE4 KEYA 1 Input/Output Input PE5 KEYB 1 Input/Output Input PE6 KEYC 1 Input/Output Input PE7 KEYD 1 Input/Output Input PF0 SO SDA 1 Input/Output Output Input/Output PF1 SI SCL 1 Input/Output Input Input/Output PF2 SCK PF3 DREQ2 1 1 Input/Output Input/Output Input/Output Input Input/Output Output Input/Output Input Input/Output Output Input/Output Input Input/Output Input Input/Output Output Input/Output Input PF4 DACK 2 1 PF5 DREQ3 1 PF6 DACK3 1 PF7 TBTIN PG0 - PG7 TC0IN - TC7IN PH0 - PH7 TCOUT0 - TCOUT7 PJ0 INT0 1 8 8 1 TMP1962-11 2006-02-21 TMP1962C10BXBG Table 2.2 Pin Names and Functions (5/6) Pin Name PJ1 BUSMD Number of Pins 1 Type Input/Output Input Function Port J1: Programmable as input or output External Bus Mode: Multiplexed Bus mode is selected if this signal is sampled high on the rising edge of the reset signal. Separate Bus mode is selected if this signal is sampled low on the rising edge of the reset signal. The BUSMD pin should be pulled up or down upon a reset according to the bus mode to be used. Port J2: Programmable as input or output Single Boot Mode: Single Boot mode is selected if this signal is sampled low on the rising edge of the reset signal. Single Boot mode is used to rewrite the contents of on-chip flash memory. Normal operation is selected if the signal is sampled high on the rising edge of the reset signal. When performing normal operation, the BOOT pin should not be pulled down upon a reset. Port J3: Programmable as input or output Interleave Mode: Interleave mode is selected if this signal is sampled high on the rising edge of the reset signal. The INTLV pin should be pulled up when using Interleave mode. Otherwise, it should be pulled down. Port J4: Programmable as input or output Endian Mode: Big-Endian mode is selected if this signal is sampled high on the rising edge of the reset signal. Little-Endian mode is selected if this signal is sampled low on the rising edge of the reset signal. Port K: Individually programmable as input or output Key-Pressed Wake-up Input 0 to 7 (with internal pull-up resistor): Dynamic pull-up selectable Schmitt-triggered input Port L0: Programmable as input or output 8-Bit Timer 4 Input: Input to 8-bit timer 4 Port L1: Programmable as input or output 8-Bit Timer 6 Input: Input to 8-bit timer 6 Port L2: Programmable as input or output 8-Bit Timer 8 Input: Input to 8-bit timer 8 Port L3: Programmable as input or output 8-Bit Timer A Input: Input to 8-bit timer A Port L4: Programmable as input or output 16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit timer 0 Port L5: Programmable as input or output 16-Bit Timer 0 Input 1: Capture trigger input to 16-bit timer 0 Port L6: Programmable as input or output 16-Bit Timer 1 Input 0: Count/capture trigger input to 16-bit timer 1 Port L7: Programmable as input or output 16-Bit Timer 1 Input 1: Capture trigger input to 16-bit timer 1 Port M: Individually programmable as input or output Port N0: Programmable as input or output Serial Transmit Data 6: Programmable as a push-pull or open-drain output Port N1: Programmable as input or output Serial Receive Data 6 Port N2: Programmable as input or output Serial Clock Input/Output 6 Serial Clear-to-Send 6: Programmable as a push-pull or open-drain output Port N3 to N7: Individually programmable as input or output Port O: Individually programmable as input or output Port P: Individually programmable as input or output PJ2 1 Input/Output Input PJ3 1 Input/Output Input PJ4 ENDIAN 1 Input/Output Input PK0 - PK7 KEY0 - KEY7 8 Input/Output Input PL0 TA4IN PL1 TA6IN PL2 TA8IN PL3 TAAIN PL4 TB0IN0 PL5 TB0IN1 PL6 TB1IN0 PL7 TB1IN1 PM0 - PM7 PN0 TXD6 PN1 RXD6 PN2 SCLK6 CTS6 1 1 1 1 1 1 1 1 8 1 1 1 Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input/Output Output Input/Output Input Input/Output Input Input PN3 - PN7 PO0 - PO7 PP0 - PP7 5 8 8 Input/Output Input/Output Input/Output TMP1962-12 2006-02-21 TMP1962C10BXBG Table 2.2 Pin Names and Functions (6/6) Pin Name NMI PLLOFF Number of Pins 1 1 1 Type Input Input Input Function Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge Schmitt-triggered input This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is used; otherwise, it should be tied to logic 0 (Schmitt-triggered input). Pull-up resistors for Ports 3 and 4 are enabled if this signal is sampled high upon a reset; otherwise, the pull-up resistors are disabled. Schmitt-triggered input Reset (with internal pull-up resistor): Initializes the whole TMP1962. Schmitt-triggered input Connection pins for a high-speed resonator Debug Reset: Signal for a DSU-ICE (Schmitt-triggered input with internal pull-up resistor) Debug Clock: Signal for a DSU-ICE Debug Enable: Signal for a DSU-ICE (Schmitt-triggered input with internal pull-up resistor) PC Trace Status: Signals for a DSU-ICE Serial Data Input/Debug Interrupt: Signal for a DSU-ICE (Schmitt-triggered input with internal pull-up resistor) Serial Data Address Output/Target PC: Signal for a DSU-ICE Test Clock Input: JTAG test signal (Schmitt-triggered input with internal pull-up resistor) Test Mode Select Input: JTAG test signal (Schmitt-triggered input with internal pull-up resistor) Test Data Input: JTAG test signal (Schmitt-triggered input with internal pull-up resistor) Test Data Output: JTAG test signal Test Reset Input: JTAG test signal (Schmitt-triggered input with internal pull-down resistor) Both BW0 and BW1 should be tied to logic 1 (Schmitt-triggered input). Input pin for high reference voltage for the A/D Converter. This pin should be connected to the AVCC pin when the A/D Converter is not used. Input pin for low reference voltage for the A/D Converter. This pin should be connected to the AVSS pin when the A/D Converter is not used. Power supply pins for the A/D Converter. These pins should always be connected to power supply even when the A/D Converter is not used. Ground pin for the A/D Converter. This pin should always be connected to ground even when the A/D Converter is not used. Test pin: This pin should be tied to ground. Flash memory access enable 1.5-V power supply pin for the oscillator Ground pin (0 V) for the oscillator 1.5-V power supply pin 2-V power supply pin 3-V power supply pins Ground pin (0 V) RSTPUP RESET 1 2 1 1 1 4 1 1 1 1 1 1 1 2 1 1 2 3 1 1 1 1 1 5 9 9 Input Input/Output Input Output Input Output Input Output Input Input Input Output Input Input Input Input Input Output X1/X2 DRESET DCLK DBGE PCST3 - 0 SDI/ DINT SDAO/TPC TCK TMS TDI TDO TRST BW0 - 1 VREFH VREFL AVCC31 - 32 AVSS TEST5 SYSRDY CVCC15 CVSS DVCC15 DVCC2 DVCC31 - 34 DVSS Note: PJ1, PJ2, PJ3 and PJ4 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of RESET, with the RESET signal being stable in either logic state. TMP1962-13 2006-02-21 TMP1962C10BXBG Table 2.3 shows the correspondence between pins and power supply pins. Table 2.3 Pins and Corresponding Power Supply Pins Pin P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO Power Supply Mask Type DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 AVCC32 AVCC32 AVCC31 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC34 DVCC2 DVCC34 DVCC34 DVCC34 DVCC31 DVCC31 Flash Type DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 AVCC32 AVCC32 AVCC31 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC34 DVCC21 DVCC34 DVCC34 DVCC34 DVCC31 DVCC31 Pin PP X1 X2 RESET NMI PLLOFF DRESET Power Supply Mask Type DVCC31 CVCC15 CVCC15 DVCC2 DVCC2 DVCC2 DVCC2 DVCC2 DVCC2 DVCC2 DVCC2 DVCC2 DVCC34 DVCC34 DVCC34 DVCC34 DVCC34 DVCC2 DVCC32 DVCC2 NC NC NC NC NC Flash Type DVCC31 CVCC2 CVCC2 DVCC21 DVCC21 DVCC21 DVCC21 DVCC21 DVCC21 DVCC21 DVCC21 DVCC21 DVCC34 DVCC34 DVCC34 DVCC34 DVCC34 DVCC21 DVCC32 FVCC2 FVCC2 FVSS FVCC FVCC2 FVSS DCLK DBGE PCST3 - 0 SDI/ DINT SDAO/TPC TCK TMS TDI TDO TRST BW1 - 0 RSTPUP G3 G18 K5 L1 L15 M15 TMP1962-14 2006-02-21 TMP1962C10BXBG Table 2.4 shows the supply voltage for power supply pins. Table 2.4 Supply Voltage for Power Supply Pins Power Supply Pin Supply Voltage DVCC15 CVCC15 DVCC2 DVCC21 DVCC22 CVCC2 FVCC2 FVCC3 DVCC31 - 34 AVCC31 - 32 1.35 V - 1.65 V 1.35 V - 1.65 V 2.3 V - 3.3 V 2.2 V - 2.7 V 2.2 V - 2.7 V 2.2 V - 2.7 V 2.2 V - 2.7 V 2.9 V - 3.6 V 1.65 V - 3.3 V 2.7 V - 3.3 V Mask/Flash Type Flash Type Mask Type Applied for Note 1: AVCC32 AVCC31 * * When P7 to P9 are used as A/D converter inputs: 2.7 V < AVCC3* When P9 (powered by AVCC31) is used as an A/D converter input while P7 and P8 (powered by AVCC32) are used as ports: 2.7 V AVCC31 3.3 V 1.65 V AVCC32 AVCC31 When P7 (powered by AVCC32) is used as an A/D converter input while P8 (powered by AVCC32) and P9 (powered by AVCC31) are used as ports: 2.7 V AVCC32 AVCC31 3.3 V * Note 2: With power supplies for CPU and internal logic (mask type: DVCC15/DVCC2/CVCC15, and flash type: DVCC21/DVCC22/CVCC2/FVCC2/FVCC3) being applied, power supplies for other I/O ports can be interrupted on TMP1962. However, when AVCC31 for analog power supply is interrupted, overlap current is generated on the TMP1962F10AXBG with on-chip flash memory during the transition to be stable in 0 V. Overlap current can be suppressed by AD conversion of the conversion result 0 V before interrupting AVCC31 power supply, but please suppress it on devices. TMP1962-15 2006-02-21 TMP1962C10BXBG 3. Core Processor The TMP1962 contains a high-performance 32-bit core processor called the TX19. For a detailed description of the core processor, refer to the TX19 Family Architecture manual. Functions unique to the TMP1962, which are not covered in the architecture manual, are described below. Note: All references to register addresses in the following descriptions assume that the TMP1962 is operating in Big-Endian mode. We recommend the power on sequence of this device ,firstly turn on a power to core (Flash: FVCC=2.5V, Mask: DVCC15=1.5V) before other power on in this device. DVCC15 (FVCC25) DVCC3(1) DVCC3(2) DVCC3(1) (2) I/O Power ADC Power 3.1 Reset Operation To reset the TMP1962, RESET must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 2.37 s at 40.5 MHz when the on-chip PLL is utilized. After a reset, either the PLL-multiplied clock or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected clock is geared down to 1/8 for internal operation. The following occurs as a result of a reset: * * The System Control Coprocessor (CP0) registers within the TX19 core processor are initialized. For details, refer to the architecture manual. The Reset exception is taken. Program control is transferred to the exception handler at a predefined address. This predefined location is called an exception vector, which directly indicates the start of the actual exception handler routine. The Reset exception is always vectored to virtual address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception). All on-chip I/O peripheral registers are initialized. All port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. * * TMP1962-16 2006-02-21 TMP1962C10BXBG Note 1: The TMP1962 must be powered up with RESET asserted. The reset state should not be terminated until after the power supply voltage stabilizes within the valid operating range. Note 2: A wait time of at least 500 s is required between the time when the power supply voltages for the stabilize and the time when the reset state is terminated. When you use the FLASH product. When the TMP1962 is powered up, terminating the reset state causes the core processor to wait 30 s before starting operation. This time is required to initialize the on-chip flash memory controller. The TMP1962 outputs the SYSRDY signal to notify an external device that the core processor has started. Once the core processor exits from the reset state, the SYSRDY signal is driven from low to high. Subsequent non-power-up reset operations are controlled with bit 7 (FLRMSK) of the Flash Control/Status Register (FLCS) in the flash memory controller. If the FLRMSK bit is cleared to 0 (default), the flash memory controller is always initialized upon a reset. Setting the FLRMSK bit to 1 prevents the flash memory controller from being initialized upon a reset (data in on-chip flash memory can still be read correctly). In the latter case, the 30 s (T.B.D.) wait time, described above, is not required after a reset so that the core processor starts immediately, driving SYSRDY high. The setting of the FLRMSK bit is held until the TMP1962 is powered off. Usually, FLRMSK should be set to 1 as part of initialization after a reset. 7 FLCS (0xFFFF_E520) 6 5 4 3 2 RDY/BSY R 1 Ready/Busy 0: Automatic operation in progress 1: Automatic operation completed 1 0 Bit symbol Read/Write Reset value Function FLRMSK W 0 Flash reset mask 0: Reset the flash memory controller. 1: Do not reset the flash memory controller. 0 Must be written as 0. (The FLCS is a 32-bit register.) Figure 3.1 Flash Control/Status Register The FLCS register doesn't exist in the mask rom type an irregular value is read when leading. TMP1962-17 2006-02-21 TMP1962C10BXBG Memory Map Figure 0.1 shows memory assignment for the TMP1962. Virtual Address 0xFFFF_FFFF 16 Mbytes Reserved 16 Mbytes Reserved On-Chip Peripherals On-Chip RAM (32 KB) Shadow Physical Address 0xFFFF_E000 0xFFFF_DFFF 0xFFFF_6000 0xFFFD_FFFF 0xFFFD_6000 0xFF3F_FFFF 0xFF20_FFFF 0xFF00_0000 Kseg2 (Cacheable) 0XBFCF_FFFF 16 Mbytes Reserved Kseg2 (1 Gbyte) (Reserved) On-Chip RAM (40 KB) 0xBFC0_0000 0xA000_0000 0x8000_0000 Kseg1 (Uncacheable) Kseg0 (Cacheable) 16 bytes Reserved On-Chip ROM Shadow (Reserved) Kuseg (2 Gbytes) Reserved for debugging (2 MB) (Reserved) 0x400F_FFFF 0x4000_0000 0x1FCF_FFFF On-Chip ROM 0x1FC0_0000 User Program Area Maskable Interrupt Area Exception Vector Area 0xFF00_0000 0x1FCF_FFFF Kuseg (Cacheable) Inaccessible 0x1FC0_0400 0x000F_FFFF 0x0000_0000 512 Mbytes 0x1FC0_0000 Figure 0.1 Memory Map Note 1: The on-chip 1-Mbyte ROM is mapped to the addresses from 0x1FC0_0000 through 0x1FCF_FFFF and the on-chip 40-Kbyte RAM is mapped to the addresses from 0xFFFD_6000 through 0xFFFD_FFFF. Note 2: The on-chip ROM is located in a linear address space beginning at physical address 0x1FC0_0000. All types of exceptions are vectored to the on-chip ROM when the BEV bit of the System Control Coprocessor's Status register is set to the default value of 1. (When BEV = 0, not all exception vectors reside in contiguous locations.) When external memory is used, the BEV bit can be cleared to 0. However, using the 32K-byte virtual address range beginning at 0x0000_0000 helps to improve code efficiency, as shown below. The shaded area starting at physical address 0x4000_0000 has a size equal to the on-chip ROM size. References to this range (mapped from the virtual address space starting at 0x0000_0000) are rerouted to the on-chip ROM. Examples: 32-bit ISA * Accessing the 0x0000_000032-KB region ADDIU SW * LUI ADDIU SW r2, r0, 7 r2, Io (_t) (r0) r3, hi (_f) r2, r0, 8 r2, Io (_f) (r3) ; r 2 (0x0000_0007) ; 0x0000_xxxx (r2) Accessed with a single instruction ; Upper 16 bits of address are loaded into r3. ; r 2 (0x0000_0008) ; Lower 16-bits of address must be added to upper 16 bits. Accessing other regions Note 3: In the TMP1962, the on-chip 40-Kbyte RAM is mapped to the addresses from 0xFFFD_6000 through 0xFFFD_FFFF. This area is shadowed to a 32-Kbyte address range from 0xFFFF_6000 through 0xFFFF_DFFF. References to this range are rerouted to the on-chip RAM. Note 4: The TMP1962 has access to only 16 Mbytes of external physical address space. The 16-Mbyte physical memory can be located anywhere within the CPU's 3.5-Gbyte physical address space through use of programmable chip select signals. However, any address references to the on-chip memory, on-chip peripheral or reserved regions override external memory access. Note 5: No instruction should be placed in the last four words of the physical address space. * * If only on-chip ROM is used: 0x1FCF_FFF0 through 0x1FCF_FFFF If ROM is added off-chip: Last four words of the memory installed in the end-user system TMP1962-18 2006-02-21 TMP1962C10BXBG 5. Clock/Standby Control The TMP1962 has the stand-by mode in which the core processor stops to reduce power consumption. Figure 5.1 shows the transition between clocking modes. Reset Reset released IDLE Mode (CPU halted) (Selectable peripheral operation) Instruction Interrupt NORMAL Mode (fc/gear value) Instruction Interrupt STOP Mode (Whole chip halted) Transition between Clock Modes Figure 5.1 Standby Mode Flow Diagram Reset Reset released PLLOFF = 1 PLL used Normal Mode fc = fpll = fosc x 3 fsys = fc/8 fsys = 3fosc/8 fperiph = fgear = fsys Figure 5.2 Default Clock Frequencies in Normal Mode fosc: fpll: fc: fgear: fsys: Clock frequency supplied via the X1 and X2 pins PLL multiplied clock frequency (x3) Clock frequency selected by the PLLOFF pin Clock frequency selected by the GEAR[1:0] bits in the clock generator's system control register (SYSCR1) System clock frequency The CPU, ROM, RAM, DMAC and INTC operate based on this system clock. On-chip peripherals operate on fsys/2. fperiph: Clock frequency selected by the FPSEL bit in the SYSCR1 (clock source for the prescalers inside on-chip peripherals) TMP1962-19 2006-02-21 TMP1962C10BXBG 5.1 Clock Generation Main System Clock * * * * A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock. The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin. When the PLL is enabled, the input clock frequency is multiplied by three. The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.) Input clock frequency Input Frequency Range Maximum Operating Frequency 40.5 MHz 5.1.1 Minimum Operating Frequency 3.75 MHz PLL ON (for both crystal and external clock) 10 to 13.5 (MHz) TMP1962-20 2006-02-21 TMP1962C10BXBG 5.1.2 Clock Source Block Diagram SYSCR0 Warm-up Timer Lock (PLL) Timer fc fperiph (To on-chip peripherals) fsys SYSCR0 ADC conversion clock fsys SYSCR0 DMAC fperiph /4 /8 /16 INTC ADC,TMRA/B/C, /2 SIO, SBI, WDT, Port On-chip peripherals: T0 On-chip peripherals (prescaler input): TMRA/B/C, SIO, SBI, SCOUT Note 1: When the clock gear is used to reduce the system clock frequency (fsys), the prescalers within on-chip peripherals must be programmed so that the prescaler output (Tn) satisfies the following relationship: Tn < fsys/2 Note 2: The prescaler clock source (T0) must not be changed while any of the peripherals to which it is supplied are running. Figure 5.3 Dual Clock and Standby Block Diagram TMP1962-21 2006-02-21 TMP1962C10BXBG 5.2 Clock Generator (CG) Registers System Clock Control Registers 31 30 SCOSEL1 5.2.1 29 SCOSEL0 28 ALESEL 27 26 R 25 LUPFG 24 LUPTM R/W 0 SYSCR3 (0xFFFF_EE00) Bit symbol Read/Write Reset value Function 0 R/W 0 1 1 ALE output width select 0: fsys x 0.5 1: fsys x 1.5 1 Must be written as 0 (flash type) 1 Must be written as 0 (flash type) 0 PLL lock SCOUT output select 00: fs 01: fsys/2 10: fsys 11: (reserved) PLL lock time 0: Locked 1: Unlocked select 0: 216/input frequency 1: 212/input frequency 23 SYSCR2 (0xFFFF_EE01) Bit symbol Read/Write Reset value Function DRVOSCH 22 21 WUPT1 20 WUPT0 R/W 0 19 STBY1 1 18 STBY0 1 17 16 DRVE R/W R/W 0 Highspeed oscillator drive capability 0: High 1: Low 0 Must be written as 0 (flash type) 1 0 0 0: Pins are not driven in STOP mode. 1: Pins are driven in STOP mode. (See Table 3.3.9.) Oscillator warm-up time (Note 2) 00: No warm-up 8 01: 2 /input frequency 14 10: 2 /input frequency 16 11: 2 /input frequency Standby mode select (Note 1) 00: Reserved 01: STOP mode 10: Reserved 11: IDLE mode 15 SYSCR1 (0xFFFF_EE02) Bit symbol Read/Write Reset value Function 0 14 13 12 FPSEL R/W 11 10 9 GEAR1 R/W 8 GEAR0 1 0 0 0 0 0 Must be written as 0 (flash type) 1 fperiph Must be written as 0 select (flash type) 0: fgear 1: fc High-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 7 SYSCR0 (0xFFFF_EE03) Bit symbol Read/Write Reset value Function 1 6 5 4 3 2 1 PRCK1 R/W 0 PRCK0 0 0 1 0 0 0 0 Must be Must be Must be Must be written as 1 written as 0 written as 1 written as 0 (flash type) (flash type) (flash type) (flash type) Must be Prescaler clock select written as 0 00: fperiph/16 01: fperiph/8 10: fperiph/4 11: (reserved) Note 1: The Config register in the CP0 has the Doze and Halt bits. Setting the Halt bit puts the TMP1962 in one of the standby modes, as specified by the STBY[1:0] bits in the SYSCR2. Setting the Doze bit puts the TMP1962 in IDLE mode, irrespective of the settings of the STBY[1:0] bits. Note 2: The WUPT[1:0] bits in the SYSCR2 must not be changed during the oscillator warm-up period. The LUPTM bit in the SYSCR3 must not be changed during the PLL lock period. Note 3: The oscillator warm-up period (WUP) timer is also used as the PLL lock timer. Note 4: When the PLL is used, the WUPT[1:0] bits in the SYSCR2 must not be set to 00 (no warm-up). Note 5: When the PLL is not used, the LUPFG bit in the SYSCR3 is always read as 0. TMP1962-22 2006-02-21 TMP1962C10BXBG 5.2.2 STOP Wake-up Interrupt Control Registers (INTCG Registers) 31 30 29 EMCG31 1 Wake-up INT3 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 0 28 EMCG30 27 26 25 24 INT3EN R/W 0 INT3 enable 0: Disable 1: Enable IMCGA0 (0xFFFF_EE10) Bit symbol Read/Write Reset value Function 23 Bit symbol Read/Write Reset value Function 22 21 EMCG21 1 Wake-up INT2 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 20 EMCG20 0 19 18 17 16 INT2EN R/W 0 INT2 enable 0: Disable 1: Enable 15 Bit symbol Read/Write Reset value Function 14 13 EMCG11 1 Wake-up INT1 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 12 EMCG10 0 11 10 9 8 INT1EN R/W 0 INT1 enable 0: Disable 1: Enable 7 Bit symbol Read/Write Reset value Function 6 5 EMCG01 1 Wake-up INT0 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 4 EMCG00 0 3 2 1 0 INT0EN R/W 0 INT0 enable 0: Disable 1: Enable TMP1962-23 2006-02-21 TMP1962C10BXBG 31 IMCGB0 (0xFFFF_EE14) Bit symbol Read/Write Reset value Function 30 29 R/W 1 . 28 27 26 25 24 R/W 1 0 Must be written as 0. 23 Bit symbol Read/Write Reset value Function 22 21 R/W 1 20 19 18 17 16 R/W 0 0 Must be written as 0. 15 Bit symbol Read/Write Reset value Function 14 13 EMCG51 0 R/W 12 EMCG50 1 11 10 9 8 KWUPEN R/W 0 KWUP enable 0: Disable 1: Enable Wake-up KWUP sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited 11: Setting prohibited These bits must be set to 01. 7 Bit symbol Read/Write Reset value Function 6 5 EMCG41 1 Wake-up INT4 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 4 EMCG40 0 3 2 1 0 INT4EN R/W 0 INT4 enable 0: Disable 1: Enable TMP1962-24 2006-02-21 TMP1962C10BXBG 31 IMCGC0 (0xFFFF_EE18) Bit symbol Read/Write Reset value Function 30 29 EMCGB1 1 Wake-up INT6 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 28 EMCGB0 0 27 26 25 24 INT6EN R/W 0 INT6 enable 0: Disable 1: Enable 23 Bit symbol Read/Write Reset value Function 22 21 EMCGA1 1 Wake-up INT5 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 20 EMCGA0 0 19 18 17 16 INT5EN R/W 0 INT5 enable 0: Disable 1: Enable 15 Bit symbol Read/Write Reset value Function 14 13 R/W 1 12 11 10 9 8 R/W 1 0 Must be written as 0. 7 Bit symbol Read/Write Reset value Function 6 5 R/W 1 4 3 2 1 0 R/W 1 0 Must be written as 0. TMP1962-25 2006-02-21 TMP1962C10BXBG 31 IMCGD0 (0xFFFF_EE1C) Bit symbol Read/Write Reset value Function 30 29 EMCGF1 1 Wake-up INTA sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 28 EMCGF0 0 27 26 25 24 INTAEN R/W 0 INTA enable 0: Disable 1: Enable 23 Bit symbol Read/Write Reset value Function 22 21 EMCGE1 1 Wake-up INT9 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 20 EMCGE0 0 19 18 17 16 INT9EN R/W 0 INT9 enable 0: Disable 1: Enable 15 Bit symbol Read/Write Reset value Function 14 13 EMCGD1 1 Wake-up INT8 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 12 EMCGD0 0 11 10 9 8 INT8EN R/W 0 INT8 enable 0: Disable 1: Enable 7 Bit symbol Read/Write Reset value Function 6 5 EMCGC1 1 Wake-up INT7 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge R/W 4 EMCGC0 0 3 2 1 0 INT7EN R/W 0 INT7 enable 0: Disable 1: Enable TMP1962-26 2006-02-21 TMP1962C10BXBG Note 1: The edge/level sensitivity must be defined for an interrupt pin which is enabled as wake-up signaling to exit STOP mode. Note 2: Interrupt programming must follow these steps: 1. Configure the pin as an interrupt input, if the pin is multiplexed with a general-purpose port. 2. Set the active state for the interrupt during initialization. 3. Clear any interrupt request. 4. Enable the interrupt. Note 3: The above steps must be performed with the relevant interrupt pin disabled. Note 4: The TMP1962 has 15 interrupt sources which can be used for wake-up signaling to exit STOP mode: INT0 to INTA, INTRTC, INTTB2, INTTB3 and KWUP0 to KWUPD. When one of INT0 to INTA is used for STOP wake-up signaling, it must be enabled as a wake-up interrupt source in the CG block and its interrupt sensitivity must be specified in the CG block. When one of KWUP0 to KWUPD is used for STOP wake-up signaling, it must be enabled as a wake-up interrupt source in the CG block and its interrupt sensitivity must be specified in the KWUPSTx. In the INTC block, the sensitivity for all of the above 15 interrupt sources must be set to the high level. Example: Enabling the INT0 interrupt IMCGA0 INTC block (Set the interrupt sensitivity to the high level, and the interrupt priority level to 5.) All interrupt sources other than those used for STOP wake-up signaling are controlled by the INTC block. Note 5: When one of INT0 to INTA is used as a normal interrupt source, its settings in the CG block are not necessary while its interrupt sensitivity must be specified in the INTC block. When one of KWUP0 to KWUPD is used as a normal interrupt source, its settings in the CG block are not necessary while its interrupt sensitivity must be specified in the KWUPSTx (in the INTC block, the sensitivity for KWUP0 to KWUPD must be set to the high level). For INTRTC, however, both CG and INTC settings are required even when it is used as a normal interrupt source. All interrupt sources other than those used for STOP wake-up signaling are controlled by the INTC block. TMP1962-27 2006-02-21 TMP1962C10BXBG 5.2.3 Exit Stop Mode Interrupt Clear Request Register (EICRCG Register) 31 30 29 28 27 26 25 24 EICRCG (0xFFFF_EE20) Bit symbol Read/Write Reset value Function 23 Bit symbol Read/Write Reset value Function 22 21 20 15 Bit symbol Read/Write Reset value Function 14 13 12 7 Bit symbol Read/Write Reset value Function 6 5 4 3 ICRCG3 0000: INT0 0001: INT1 0010: INT2 0011: INT3 0100: INT4 2 ICRCG2 W 0101: KWUP 1 ICRCG1 0 ICRCG0 Clear interrupt request 1010: INT5 0110: reserved 1011: INT6 0111: reserved 1100: INT7 1000: reserved 1101: INT8 1001: reserved 1110: INT9 1111: INTA Note 6: Interrupt requests for the above 15 interrupt sources which can be used for wake-up signaling to exit STOP mode are cleared as follows: 1. The clearing of KWUP interrupt sources is controlled through the KWUPCLR register. 2. Clearing the INT0 to INTA, INTTB2, INTTB3 and INTRTC interrupt requests requires two register settings: first, the EICRCG register in the CG block, and then the INTCLR register in the INTC block. 3. The clearing of other interrupt sources is controlled through the INTCLR register alone. TMP1962-28 2006-02-21 TMP1962C10BXBG 5.3 System Clock Control Section A system reset initializes the SYSCR0.XEN bit to 1, the SYSCR0.XTEN bit to 0 and the SYSCR1.GEAR[1:0] bits to 11, putting the TMP1962 in Single-Clock mode. If the on-chip PLL is enabled, the PLL reference clock is always multiplied by three. By default, the system clock frequency (fsys) is geared down to fc/8, where fc = fosc x 3 (fosc is the oscillator frequency). For example, if a 13.5-MHz crystal is connected between the X1 and X2 pins, the fsys clock operates at 5.0625 MHz (13.5 x 3 x 1/8). Note: The system clock frequency must be initialized to 3.75 MHz or higher. 5.3.1 Oscillation Stabilization Time When a crystal is connected between the X1 and X2 pins and/or XT1 and XT2 pins, the integrated warm-up period timer is used to assure oscillation stability. The warm-up period can be selected through the [WUPT1:0] bits of the SYSCR2 to suit the crystal used. Table 5.1 shows the warm-up periods required when the clocking is switched between NORMAL and SLOW modes. Note 1: No warm-up is necessary when the TMP1962 is driven by an external oscillator clock which is already stable. Note 2: Because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations will lead to small timer errors. Table 5.1 should be considered as approximate values. Table 5.1 Warm-up Periods Warm-up Period Select SYSCR2.WUPT[1:0] 01 (2 /oscillation frequency) 10 (2 /oscillation frequency) 11 (2 /oscillation frequency) 16 14 8 High-Speed Clock (fosc) 19.0 (s) 1.214 (ms) 4.855 (ms) Assumption: fosc = 13.5 MHz TMP1962-29 2006-02-21 TMP1962C10BXBG 5.3.2 System Clock Output The fsys, fsys/2 or fs clock can be driven out from the P44/SCOUT pin. The P44/SCOUT pin is configured as SCOUT (system clock output) by programming the Port 4 registers as follows: P4CR.P44C = 1 and P4FC.P44F = 1. The output clock is selected through the SYSCR3.SCOSEL[1:0] bits. Table 5.2 shows the pin states in each clocking mode when the P44/SCOUT pin is configured as SCOUT. Table 5.2 SCOUT Output States Mode SCOUT Select NORMAL, SLOW The fsys/2 clock is driven out. The fsys clock is driven out. Standby Modes IDLE STOP Held at either 1 or 0. Note: The phase difference between the system clock output signal (SCOUT) and the internal clock signal cannot be guaranteed. 5.3.3 Reducing the Oscillator Clock Drive Capability When a crystal is connected between the X1 and X2 pins and/or between XT1 and XT2 pins, oscillator noise and power consumption can be reduced through the programming of the SYSCR2. Setting the SYSCR2.DRVOSCH bit reduces the drive capability of the high-speed oscillator. Setting the SYSCR2.DRVOSCL bit reduces the drive capability of the low-speed oscillator clock. A reset clears both the DRVOSCH and DRVOSCL bits to 0, providing a high drive capability at power-up. Both the high-speed and low-speed oscillator clocks must have a high drive capability (i.e., DRVOSCH = 0, DRVOSCL = 0) when clocking modes are changed. * Drive capability of the high-speed oscillator fOSC C1 Crystal C2 X2 Pin X1 Pin Oscillation Enable SYSCR2 Figure 5.4 Oscillator Clock Drive Capabilities TMP1962-30 2006-02-21 TMP1962C10BXBG 5.4 Prescaler Clock Control Section The TMRA01 to TMRAAB, TMRB0 to TMRB3, TMRC, SIO0 to SIO6 and SBI have a clock prescaler. The prescaler clock source (T0) can be selected from fperiph/16, fperiph/8 and fperiph/4 through the PRCK[1:0] bits of the SYSCR0. fperiph can be selected from either fgear or fc through the FPSEL bit of the SYSCR1. The default reset values select fgear as fperiph, and fperiph/16 as T0. 5.5 Clock Frequency Multiplication Section (PLL) The on-chip PLL multiplies the frequency of the high-speed oscillator clock (fosc) by three to generate the fpll clock. To use the PLL, the PLLOFF pin must be high when RESET is released. Being an analog circuit, the PLL requires a certain duration of time (called lock time) to stabilize, like an oscillator. The oscillator warm-up period (WUP) timer is also used as the PLL lock timer. The LUPTM bit in the SYSCR3 must be programmed so that the following relationship is satisfied: PLL lock time Oscillator warm-up time At reset, the default lock-up time is 216/input frequency. Setting the WUP timer control bit (SYSCR0.WUEF) starts the PLL lock timer. The SYSCR3.LUPTM bit remains set while the PLL is out of lock, and is cleared when the PLL locks. In real-time applications whose software execution time is critical, once the PLL has gone out of lock in a standby mode, software must determine before resuming operation whether the PLL has locked (after the oscillator warm-up time has expired) in order to assure clock stability. Note 1: If the PLLOFF pin is low when RESET is released, the PLL will be disabled and the oscillator clock will be driven with no frequency multiplication. Note 2: The following must be noted when changing the clock gear value. The clock gear can be changed by the programming of the GEAR[1:0] bits of the SYSCR1. It takes a few clock cycles for a gear change to take effect. Therefore, one or more instructions following the instruction that changed the clock gear value may be executed using the old clock gear value. If subsequent instructions need to be executed with a new clock gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that modifies the clock gear value. When the clock gear is used, the prescalers within on-chip peripherals must be programmed so that the prescaler output (Tn) satisfies the following relationship: Tn < fsys/2 The clock gear must not be changed while a timer/counter or other peripherals are operating. TMP1962-31 2006-02-21 TMP1962C10BXBG 5.6 Standby Control Section The TMP1962 provides support for several levels of power reduction. While in NORMAL mode, setting the Halt bit of the Config register within the TX19 core processor causes the TMP1962 to enter one of the standby modes -- IDLE, STOP -- as specified by the SYSCR2.STBY[1:0] bits. Setting the Doze bit of the Config register causes the TMP1962 to enter IDLE (Doze) mode, irrespective of the setting of SYSCR2.STBY[1:0]. The characteristics of the IDLE, STOP modes are as follows: IDLE: The CPU stops. On-chip peripherals can be selectively enabled and disabled through use of a register bit in a given peripheral, as shown in Table 5.3. If an on-chip peripheral has its register bit cleared to disable operation in IDLE mode, it stops when the TMP1962 enters IDLE mode, holding the state in which it is placed when it stops. Table 5.3 IDLE Mode Register Settings Peripheral TMRA01 to AB TMRB0 to 3 TBT SIO0 to 6 SBI A/D Converter WDT IDLE Mode Bit TAxxRUN Note 1: In Halt mode (i.e., a standby mode entered by setting the Halt bit in the Config register), the TMP1962 freezes the TX19 core processor, preserving the pipeline state. In Halt mode, the TMP1962 ignores any external bus requests; so it continues to assume bus mastership. Note 2: In Doze mode (i.e., a standby mode entered by setting the Doze bit in the Config register), the TMP1962 freezes the TX19 core processor, preserving the pipeline state. In Doze mode, the TMP1962 recognizes external bus requests. STOP: The whole TMP1962 stops. TMP1962-32 2006-02-21 TMP1962C10BXBG 5.6.1 TMP1962 Operation in NORMAL and Standby Modes Table 5.4 TMP1962 Operation in NORMAL and Standby Modes Operating Mode NORMAL IDLE (Halt) IDLE (Doze) STOP Operating States The TX19 core processor and on-chip peripherals operate at frequencies specified in the CG block. The processor and DMAC operations stop; other on-chip peripherals can be selectively disabled. Processor operation stops; the DMAC is operational; other on-chip peripherals can be selectively disabled. All processor and peripheral operations stop completely. 5.6.2 CG Operation in NORMAL and Standby Modes Table 5.5 CG States in NORMAL and Standby Modes Clock Source Crystal Mode Normal Idle (Halt) Idle (Doze) Stop Oscillator x x x x x PLL x x Clock Supply to Peripherals Selectable Selectable x Selectable Selectable x Clock Supply to CPU x x x x x x External Clock Normal Idle (Halt) Idle (Doze) Stop : Operational, or clock supplied x. Stopped, or clock not supplied TMP1962-33 2006-02-21 TMP1962C10BXBG 5.6.3 Processor and Peripheral Block Operation in Standby Modes Table 5.6 Processor and Peripheral Blocks in Standby Modes Circuit Block Clock Source IDLE (Doze) x fsys IDLE (Halt) x x x x x STOP x x x x x x x x x TX19 Core Processor DMAC INTC External Bus Interface External Bus Mastership I/O Ports ADC SIO IC TMRA TMRB TMRC WDT 2-Phase Pulse Input Counter CG : On x: Off 2 Selectable on a block-by-block basis x x x x x x 5.6.4 Wake-up Signaling There are two ways to exit a standby mode: an interrupt request or a reset signal. Availability of wakeup signaling depends on the settings of the Interrupt Mask Level bits, CMask[15:13], of the CP0 Status register and the current standby mode (see Table 5.7). * Wake-up via Interrupt Signaling The operation upon return from a standby mode varies, depending on the interrupt priority level programmed before entering a standby mode. If the interrupt priority level is greater than or equal to the processor's interrupt mask level, execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated the standby mode (i.e., the instruction that set the Halt or Doze bit in the Config register). If the interrupt priority level is less than the processor's interrupt mask level, program execution resumes with the instruction that activated the standby mode. The interrupt is left pending. Nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the current interrupt mask level. * Wake-up via Reset Signaling Reset signaling always brings the TMP1962 out of any standby mode. A wake-up from STOP mode must, however, allow sufficient time for the oscillator to restart and stabilize (see Table 5.1). A reset does not affect the contents of the on-chip RAM, but initializes everything else, whereas an interrupt preserves all internal states that were in effect before the standby mode was entered. TMP1962-34 2006-02-21 TMP1962C10BXBG For details of STOP wake-up interrupts and other normal interrupts, refer to Chapter 6, "Interrupts." Table 5.7 Wake-up Signaling Sources and Wake-up Operations Interrupt Masking Standby Mode NMI Unmasked Interrupt (request_level > mask_level) IDLE (Programmable) Masked Interrupt (request_level mask_level) IDLE (Programmable) STOP (Note 1) x (Note 1) (Note 1) x x x x x STOP (Note 1) x (Note 1) (Note 1) x x x x x Wake-up Signaling Sources INTWDT INT0 to A Interrupts KWUP0 to D INTTB0 to 3 INTTA0 to D INTRX0 to 6, TX0 to 6 INTS INTAD/ADHP/ADM RESET : Execution resumes with the interrupt service routine. (RESET initializes the whole TMP1962.) : Execution resumes with the instruction that activated the standby mode. The interrupt is left pending. x: Cannot be used to exit a standby mode. Note 1: The TMP1962 exits the stanby mode after the warm-up period timer expires. Note 2: If the interrupt request level is greater than the mask level, an interrupt signal which is programmed as level-sensitive must be held active until interrupt processing begins. Otherwise, the interrupt will not be serviced successfully. Note 3: If interrupts are disabled in the CPU, all interrupts other than those used for wake-up signaling must also be disabled in the Interrupt Controller (INTC) before a stanby mode is entered. Otherwise, any interrupt could take the TMP1962 out of the stanby mode. TMP1962-35 2006-02-21 TMP1962C10BXBG 5.6.5 STOP Mode The STOP mode stops the whole TMP1962, including the on-chip oscillator. Pin states in STOP mode depend on the setting of the SYSCR2.DRVE bit, as shown in Table 5.8. Upon detection of wake-up signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to restart and stabilize before exiting STOP mode. After that, the system clock output can restart. On exiting STOP mode, the TMP1962 starts operation in the mode (NORMAL or SLOW) in which it was in before entering STOP mode. Applicable register bits must be programmed prior to the instruction that activates a standby mode. The warm-up period is chosen through the SYSCR2.WUPT[1:0] bits. Note: In the TMP1962F10AXB, the SYSCR2.WUPT[1:0] bits (warm-up time) must not be set to 00 or 01 when the mode is changed from NORMAL to STOP, because this does not allow enough time (at least 150 s) for the internal system to resume when the TMP1962 exits STOP mode. 5.6.6 Returning from STOP Mode (1) Mode transitions from NORMAL to STOP to NORMAL fsys (High-speed clock) Mode NORMAL CG (High-speed clock) System clock stopped STOP NORMAL Warm-up (W-up) High-speed clock oscillator started Warm-up started Warm-up completed When fosc = 13.5 MHz W-up Time Select SYSCR2.WUPT[1:0] 01 (2 /fosc) 10 (2 /fosc) 11 (2 /fosc) 16 14 8 W-up Time (fosc) Setting prohibited 1.214 ms 4.855 ms Note: The WUPT[1:0] bits must not be set to 01 because this does not allow enough time for the internal system to resume. TMP1962-36 2006-02-21 TMP1962C10BXBG Table 5.8 Pin States in STOP Mode (1/2) Pins P00 to P07 Input/Output Input mode Output mode AD0 to AD7, D0 to D7 Input mode Output mode, A8 to A15 AD8 to AD15, D8 to D15 Input mode Output mode, A0 to A7/A16 to A23 Output pin Input mode Output mode Input mode Output mode ALE (Output mode) Input mode Output mode Input mode Output mode Input mode Output mode, A0 to A7 Input mode Output mode, A8 to A15 Input pin Input mode Output mode Input mode Output mode Input mode Output mode INT5 to INT8 (Input mode) Input mode Output mode Input mode Output mode Input mode Output mode KEY8 (Input mode) Input mode Output mode Input mode Output mode KEY9 to KEYD (Input mode) Input mode Output mode Input mode Output mode INT1 to 4,INT9,INTA (Input mode) Input mode Output mode INT0 (Input mode) Input mode Output mode Input mode Output mode KEY0 to KEY7 (Input mode) SYSCR2. DRVE = 0 PU* PU* Output Low PU* PU* Input Input Input Input Input Input SYSCR2. DRVE = 1 Output Output Output Output Input Output Input Output Output Low Input Output Input Output Output Output Input Output Input Output Input Output Input Input Output Input Output Input Output Input Input Output Input Output Input Input Output Input Output Input Input Output Input Input Output Input Output Input P10 to P17 P20 to P27 P30 (/RD), P31 (/WR) P32 to P36 P37 (ALE) P40 to P43 P44 (SCOUT) P50 to P57 P60 to P67 P7, P8, P9 PA0 to PA7 PB0, PB1, PB4, PB7 PB2, PB3, PB5, PB6 PC0 to PC7 PD0 to PD6 PD7 PE0 to PE2 PE3 to PE7 PF, PG, PH, PI0, PI7 PI1 to PI6 PJ0 PJ1 to PJ4 PK0 to PK7 TMP1962-37 2006-02-21 TMP1962C10BXBG Table 5.8 Pin States in STOP Mode (2/2) Pins PL, PM, PN, PO, PP NMI RESET Input/Output Input mode Output mode Input pin Input pin Input pin Input pin Input pin Output pin Input pin Output pin SYSCR2. DRVE = 0 Input Input Input Input Input Output High Output High SYSCR2. DRVE = 1 Input Output Input Input Input Input Input Output High Output High BM0, BM1 PLLOFF RSTPUP SYSRDY X1 X2 : Input: Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and output-only pins assume the high-impedance state. The input gate is active; the input voltage must be held at either the high or low level to keep the input pin from floating. Output: Pin direction is output. PU*: Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in high-impedance state. TMP1962-38 2006-02-21 TMP1962C10BXBG 6. Interrupts Interrupt processing is coordinated between the CP0 Status register, the Interrupt Controller (INTC) and the Clock Generator (CG). The Status register contains the Interrupt Mask Level field (CMask[15:13]) and the Interrupt Enable bit (IEc). For interrupt processing, also refer to Chapter 9, "Exception Handling" in the TX19 Architecture manual. The TMP1962 interrupt mechanism includes the following features: * * * * * * 4 CPU internal interrupts (software interrupts) 26 external interrupt pins ( NMI , INT0-INTA, KWUP0-KWUPD) 56 on-chip peripheral interrupts (including a WDT interrupt) Vector generation for each interrupt source Programmable priority for each interrupt source (7 levels) DMA trigger on interrupt TMP1962-39 2006-02-21 TMP1962C10BXBG CG 12 INTnEN Standby Wakeup Control IMCGxx Register Interrupt Detection Block 11 INT0 - INTA INTC Active High Level 12 High/Low Level/Edge Select IMCxx Register High Level 12 1 Core Status Register 12 Other Interrupts Active High Level KWUP High/Low Level/Edge Select Input Enable/Disable for Each Interrupt Source KEY0 - KEYD KWUPST0 - D Register KWUP Note: There are interrupt enable and polarity bits in these registers: 1. Interrupt Mode Control registers (IMCxx) in the INTC 2. IMCGxx registers in the CG 3. KWUP Status registers (KWUPSTx) in the KWUP Figure 6.1 General Interrupt Mechanism TMP1962-40 2006-02-21 TMP1962C10BXBG (1) External interrupts INT0-INT4, KWUP0-KWUPD, INTRTC, INTTB2 and INTTB3 (2-phase pulse input counter) 1) * * * * * * INT0-INTA When enabled for STOP wake-up signaling The EMCGxx field in the CG's IMCGxx register defines the interrupt polarity. (Refer to Section 5.2.2, "INTCG Registers.") The INTxEN bit in the CG's IMCGxx register controls whether these interrupt sources are enabled as wake-up signal sources (1 = enable). (Refer to Section 5.2.2, "INTCG Registers.") If enabled, the interrupt polarity (EIMxx) field in the INTC's IMCxx register has no effect, but must be set to 01, or high level. (Refer to Section 6.4, "INTC Registers.") When disabled for STOP wake-up signaling The interrupt polarity (EIMxx) field in the INTC's IMCxx register defines the interrupt polarity. (Refer to Section 6.4, "INTC Registers.") 2) * KWUP0-KWUPD When enabled for STOP wake-up signaling * * * * The EMCG5[1:0] field in the CG's IMCGB0 register has no effect, but must be set to 01, or high level. (Refer to Section 5.2.2, "INTCG Registers.") The KWUPEN bit in the CG's IMCGB0 register controls whether these interrupt sources are enabled as wake-up signal sources (1 = enable). (Refer to Section 5.2.2, "INTCG Registers.") The interrupt polarity (EIM6[1:0]) field in the INTC's IMC1 register has no effect, but must be set to 01, or high level. (Refer to Section 6.4, "INTC Registers.") For each of these interrupt sources, the KWUPSTx register in the KWUP block defines the interrupt polarity and controls whether interrupts are enabled. When disabled for STOP wake-up signaling * * The interrupt polarity (EIM6[1:0]) field in the INTC's IMC1 register has no effect, but must be set to 01, or high level. (Refer to Section 6.4, "INTC Registers.") For each of these interrupt sources, the KWUPSTx register in the KWUP block defines the interrupt polarity and controls whether interrupts are enabled. * TMP1962-41 2006-02-21 TMP1962C10BXBG (2) Internal interrupts (except INTRTC and INTTB2/INTTB3 in 2-Phase Pulse Count mode) These interrupts are programmable through the INTC. The INTC collects interrupt events, prioritizes them and presents the highest-priority request to the TX19 core processor. Interrupt INT0 - INTA Programming IMCGx CG IMCx INTC reg.In reg.In Interrupt Sensing When enabled for STOP wake-up signaling, the polarity field in the INTC has no effect, but must always be set to "high-level." The actual sensitivity is programmed in the CG. When disabled for STOP wake-up signaling, interrupt sensitivity is programmed in the INTC. In either case, each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. The polarity field in the INTC has no effect, but must always be set to "high-level." When enabled for STOP wake-up signaling, the polarity field in the CG has no effect, but must always be set to "high-level." The actual sensitivity is programmed in the KWUPnST. When disabled for STOP wake-up signaling, the CG need not be programmed. In either case, each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. Falling edge Rising edge KWUP0 - KWUPD IMCGx reg.In CG IMCx reg.In INTC KWUPSTn On-Chip Peripherals INTDMAn Others IMCx INTC IMCx INTC reg.In reg.In * Example register settings Here are example register settings required to enable and disable the INT0 interrupt as a source of the STOP wake-up signal (negative-edge triggered). a. Enabling the interrupt IMCGA0 b. Disabling the interrupt Status TMP1962-42 2006-02-21 TMP1962C10BXBG 6.1 Interrupt Sources The TMP1962 provides a reset interrupt, nonmaskable interrupts, and maskable interrupts: (1) Reset and nonmaskable interrupts The RESET pin causes a Reset interrupt. The NMI pin functions as a nonmaskable interrupt. The on-chip Watchdog Timer (WDT) is also capable of being a source of a nonmaskable interrupt (INTWDT). Reset and nonmaskable interrupts are always vectored to virtual address 0xBFC0_0000. (2) Maskable interrupts The TMP1962 supports two types of maskable interrupts: software and hardware interrupts. Maskable interrupts are vectored to virtual addresses 0xBFC0_0210 through 0xBFC0_0260, as shown below. Interrupt Source Reset Nonmaskable Software Maskable Swi0 Swi1 Swi2 Swi3 Hardware 0xBFC0_0210 0xBFC0_0220 0xBFC0_0230 0xBFC0_0240 0xBFC0_0260 Virtual Vector Address 0xBFC0_0000 Note 1: The above table shows the vector addresses when the BEV bit in the CP0 Status register is set to 1. When BEV = 1, all exception vectors reside in the on-chip ROM space. Note 2: Software interrupts are posted by setting one of the Sw[3:0] bits in the CP0 Cause register. Software interrupts are distinct from the "Software Set" interrupt which is one of the hardware interrupt sources. A Software Set interrupt is posted from the INTC to the TX19 core processor when the IL0[2:0] field in the INTC's IMC0 register is set to a non-zero value. TMP1962-43 2006-02-21 TMP1962C10BXBG Table 6.1 Hardware Interrupt Sources Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 IVR[9 : 0] 000 010 020 030 040 050 060 070 080 090 0A0 0B0 0C0 0D0 0E0 0F0 100 110 120 130 140 150 160 170 180 190 1A0 1B0 1C0 1D0 1E0 1F0 200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0 Interrupt Source Software Set INT0 pin INT1 pin INT2 pin INT3 pin INT4 pin KWUP reserved INTRX6: SIO receive (channel.6) INTTX6: SIO transmit (channel.6) INT5 pin INT6 pin INT7 pin INT8 pin INT9 pin INTA pin INTRX0: SIO receive (channel.0) INTTX0: SIO transmit (channel.0) INTRX1: SIO receive (channel.1) INTTX1: SIO transmit (channel.1) INTS0: Serial Bus Interface 0 INTRX2: SIO receive (channel.2) INTTX2: SIO transmit (channel.2) INTADHP: High-priority A/D conversion complete INTADM: A/D conversion monitoring INTTAG0: 8-bit timer group 0 INTTAG1: 8-bit timer group 1 INTTAG2: 8-bit timer group 2 reserved INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 1 INTRX3: SIO receive (channel.3) INTTX3: SIO transmit (channel.3) INTRX4: SIO receive (channel.4) INTTX4: SIO transmit (channel.4) INTRX5: SIO receive (channel.5) INTTX5: SIO transmit (channel.5) reserved reserved reserved INTCAPG0:Input capture group 0 INTCAPG1:Input capture group 1 reserved INTCMP0: Compare 0 INTCMP1: Compare 1 INTCMP2: Compare 2 INTCMP3: Compare 3 INTCMP4: Compare 4 INTCMP5: Compare 5 INTTB2: 16-bit timer 2 INTTB3: 16-bit timer 3 INTCMP6: Compare 6 INTCMP7: Compare 7 reserved INTDMA0: DMA complete (Channel 0) INTDMA1: DMA complete (Channel 1) INTDMA2: DMA complete (Channel 2) INTDMA3: DMA complete (Channel 3) reserved INTAD: A/D conversion complete INTDMA4: DMA complete (Channel 4) INTDMA5: DMA complete (Channel 5) INTDMA6: DMA complete (Channel 6) INTDMA7: DMA complete (Channel 7) Interrupt Control Register IMC0 Address 0xFFFF_E000 IMC1 0xFFFF_E004 IMC2 0xFFFF_E008 IMC3 0xFFFF_E00C IMC4 0xFFFF_E010 IMC5 0xFFFF_E014 IMC6 0xFFFF_E018 IMC7 0xFFFF_E01C IMC8 0xFFFF_E020 IMC9 0xFFFF_E024 IMCA 0xFFFF_E028 IMCB 0xFFFF_E02C IMCC 0xFFFF_E030 IMCD 0xFFFF_E034 IMCE 0xFFFF_E038 IMCF 0xFFFF_E03C TMP1962-44 2006-02-21 TMP1962C10BXBG 6.2 Interrupt Detection When enabled as a STOP wake-up signal, the polarities of INT0-INT4 are programmed in the EMCGxx field of the IMCGxx register within the CG; in this case, the EIMxx field of the IMCx register within the INTC has no effect; however, it must be set to "high-level sensitive". For each of KWUP0-KWUPD, the KWUPSTn register within the KWUP block defines the interrupt polarity and controls whether interrupts are enabled. The EMCG field of the IMCGB register within the CG and the EIMxx field of the IMCx register within the INTC have no effect; however, they must be set to "high-level sensitive". The polarity of INTRTC must be configured as "rising-edge triggered" in the EMCGxx field of the IMCGxx register within the CG; in this case, the EIMxx field of the IMCx register within the INTC has no effect; however, it must be set to "high-level sensitive". All other interrupts are always programmed in the EMCGxx field of the INTC's IMCx register. Each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. When a selected transition is detected, an interrupt request is issued to the INTC (except for the NMI and INTWDT interrupts, which are directly delivered to the TX19 core processor). When the above interrupts are disabled for STOP wake-up signaling, the CG need not be programmed. When INT0-INTA are disabled for wake-up signaling, only the INTC has to be programmed. When KWUP0-KWUPD are disabled for wake-up signaling, only the INTC and KWUPSTx have to be programmed. It is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and to clear the interrupt condition. INT0-INTA and INTRC require software access to two registers: the EICRCG register (ICRCG field) in the CG and the INTCLR register (EICLR field) in the INTC. KWUP0-KWUPD require software access to the KWUPCLR. Other interrupts can be cleared by writing their assigned value to the EICLR field in the INTC's INTCLR register. For an external interrupt configured as level-sensitive, software must explicitly address the device in question and clear the interrupt condition. A level-sensitive interrupt signal must be held active until the TX19 core processor reads its interrupt vector from the Interrupt Vector Register (IVR). Note: To use an interrupt for wake-up signaling, define the polarity, clear the interrupt request and then enable the interrupt, always in the stated order. (Example register settings required to enable the INT0 interrupt as a source of the STOP wake-up signal) IMCGA0 TMP1962-45 2006-02-21 TMP1962C10BXBG 6.3 Resolving Interrupt Priority (1) Seven interrupt priority levels The Interrupt Mode Control registers (IMCx) contain a 3-bit interrupt priority level (ILx[2:0]) field for each interrupt source, which ranges from level 0 to level 7, with level 7 being the highest priority. Level 0 indicates that the interrupt is disabled. (2) Interrupt level notification When an interrupt event occurs, the INTC sends its priority level to the TX19 core processor. The processor can determine the priority level of an interrupt being requested by reading the IL field in the CP0 Cause register. If multiple interrupt events having different priority levels occur simultaneously, the INTC sends the highest priority level. (3) Interrupt vector (interrupt source notification) Whenever an interrupt request is made, the INTC automatically sets its vector in the IVR. The TX19 core processor can determine the exact cause of an interrupt by reading the IVR. If multiple interrupt requests occur at the same level, the interrupt with the smallest interrupt number is delivered. When no interrupt is pending, the IVR[9:4] field in the IVR contains a value of zero. When the TX19 core processor responds to a request with an interrupt acknowledge cycle, the INTC forwards the interrupt vector for that interrupt request. At this time, the TX19 core processor saves the priority level value in the CMask field of the CP0 Status register. TMP1962-46 2006-02-21 TMP1962C10BXBG 6.4 Register Description Table 6.2 INTC Register Map Address 0xFFFF_E060 0xFFFF_E040 0xFFFF_E03C 0xFFFF_E038 0xFFFF_E034 0xFFFF_E030 0xFFFF_E02C 0xFFFF_E028 0xFFFF_E024 0xFFFF_E020 0xFFFF_E01C 0xFFFF_E018 0xFFFF_E014 0xFFFF_E010 0xFFFF_E00C 0xFFFF_E008 0xFFFF_E004 0xFFFF_E000 Symbol INTCLR IVR IMCF IMCE IMCD IMCC IMCB IMCA IMC9 IMC8 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 Register Name Interrupt Request Clear Control Register Interrupt Vector Register Interrupt Mode Control Register F Interrupt Mode Control Register E Interrupt Mode Control Register D Interrupt Mode Control Register C Interrupt Mode Control Register B Interrupt Mode Control Register A Interrupt Mode Control Register 9 Interrupt Mode Control Register 8 Interrupt Mode Control Register 7 Interrupt Mode Control Register 6 Interrupt Mode Control Register 5 Interrupt Mode Control Register 4 Interrupt Mode Control Register 3 Interrupt Mode Control Register 2 Interrupt Mode Control Register 1 Interrupt Mode Control Register 0 Corresponding Interrupt Number ALL (63 - 0) ALL (63 - 0) 63 - 60 59 - 56 55 - 52 51 - 48 47 - 44 43 - 40 39 - 36 35 - 32 31 - 28 27 - 24 23 - 20 19 - 16 15 - 12 11 - 8 7-4 3-0 6.4.1 Interrupt Vector Register (IVR) This register indicates the vector for the interrupt source when there is an interrupt event. 31 30 29 28 R/W 0 0 0 0 0 0 0 0 27 26 25 24 IVR (0xFFFF_E040) Bit Symbol Read/Write Reset Value Function 23 Bit Symbol Read/Write Reset Value Function 0 22 21 20 R/W 19 18 17 16 0 0 0 0 0 0 0 15 Bit Symbol Read/Write Reset Value Function 0 14 13 R/W 12 11 10 9 IVR9 R 8 IVR8 0 0 0 0 0 0 0 Interrupt vector for the source of the current interrupt 7 Bit Symbol Read/Write Reset Value Function 0 IVR7 6 IVR6 0 5 IVR5 0 4 IVR4 R 0 3 2 1 0 0 0 0 0 Interrupt vector for the source of the current interrupt TMP1962-47 2006-02-21 TMP1962C10BXBG 6.4.2 Interrupt Mode Control Registers These registers control the interrupt priority level, active polarity, either level or edge sensitivity, and DMA triggering. 31 IMC0 (0xFFFF_E000) Bit Symbol Read/Write Reset Value Function 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 DMA trigger Interrupt sensitivity 30 29 EIM31 28 EIM30 27 DM3 R/W 26 IL32 0 25 IL31 0 24 IL30 0 When DM3 = 0 Interrupt number 3 (INT2) priority 0: Disable level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM3 = 1 3 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM21 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 20 EIM20 0 19 DM2 R/W 0 DMA trigger 18 IL22 0 17 IL21 0 16 IL20 0 Interrupt sensitivity When DM2 = 0 Interrupt number 2 (INT1) priority 0: Disable level 000: Interrupt disabled 1: Enable interrupt 001-111: 1-7 number When DM2 = 1 2 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM11 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 12 EIM10 0 11 DM1 R/W 0 10 IL12 0 9 IL11 0 8 IL10 0 Interrupt sensitivity When DM1 = 0 DMA trigger Interrupt number 1 (INT0) priority 0: Disable level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM1 = 1 1 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM01 0 00: Low level 4 EIM00 0 3 DM0 R/W 0 DMA trigger 2 IL02 0 1 IL01 0 0 IL00 0 Interrupt sensitivity 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited Must be set to 00. When DM0 = 0 Interrupt number 0 (Software Set) 0: Disable priority level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM0 = 1 0 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 TMP1962-48 2006-02-21 TMP1962C10BXBG 31 IMC1 (0xFFFF_E004) Bit Symbol Read/Write Reset Value Function 30 29 EIM71 0 28 EIM70 0 27 DM7 R/W 0 Must be set to 0. 26 IL72 0 25 IL71 0 24 IL70 0 Must be set to 00. Must be set to 000. 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM61 0 20 EIM60 0 19 DM6 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 6 as DMA trigger 18 IL62 0 When DM6 = 0 17 IL61 0 16 IL60 0 Interrupt sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited 11: Setting prohibited Must be set to 01. Interrupt number 6 (KWUP) priority level 000: Interrupt disabled 001-111: 1-7 When DM6 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM51 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 12 EIM50 0 11 DM5 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 5 as DMA trigger 10 IL52 0 When DM5 = 0 9 IL51 0 8 IL50 0 Interrupt sensitivity Interrupt number 5 (INT4) priority level 000: Interrupt disabled 001-111: 1-7 When DM5 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM41 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 4 EIM40 0 3 DM4 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 4 as DMA trigger 2 IL42 0 When DM4 = 0 1 IL41 0 0 IL40 0 Interrupt sensitivity Interrupt number 4 (INT3) priority level 000: Interrupt disabled 001-111: 1-7 When DM4 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-49 2006-02-21 TMP1962C10BXBG 31 IMC2 (0xFFFF_E008) Bit Symbol Read/Write Reset Value Function 30 29 EIMB1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 28 EIMB0 0 27 DMB R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 11 as DMA trigger 26 ILB2 0 When DMB = 0 25 ILB1 0 24 ILB0 0 Interrupt sensitivity Interrupt number 11 (INT6) priority level 000: Interrupt disabled 001-111: 1-7 When DMB = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIMA1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 20 EIMA0 0 19 DMA R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 10 as DMA trigger 18 ILA2 0 When DMA = 0 17 ILA1 0 16 ILA0 0 Interrupt sensitivity Interrupt number 10 (INT5) priority level 000: Interrupt disabled 001-111: 1-7 When DMA = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM91 0 12 EIM90 0 11 DM9 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 9 as DMA trigger 10 IL92 0 When DM9 = 0 9 IL91 0 8 IL90 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 9 (INTTX6) priority level 000: Interrupt disabled 001-111: 1-7 When DM9 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM81 0 4 EIM80 0 3 DM8 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 8 as DMA trigger 2 IL82 0 When DM8 = 0 1 IL81 0 0 IL80 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 8 (INTRX6) priority level 000: Interrupt disabled 001-111: 1-7 When DM8 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-50 2006-02-21 TMP1962C10BXBG 31 IMC3 (0xFFFF_E00C) Bit Symbol Read/Write Reset Value Function 30 29 EIMF1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 28 EIMF0 0 27 DMF R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 15 as DMA trigger 26 ILF2 0 When DMF = 0 25 ILF1 0 24 ILF0 0 Interrupt sensitivity Interrupt number 15 (INTA) priority level 000: Interrupt disabled 001-111: 1-7 When DMF = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIME1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 20 EIME0 0 19 DME R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 14 as DMA trigger 18 ILE2 0 When DME = 0 17 ILE1 0 16 ILE0 0 Interrupt sensitivity Interrupt number 15 (INT9) priority level 000: Interrupt disabled 001-111: 1-7 When DME = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIMD1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 12 EIMD0 0 11 DMD R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 13 as DMA trigger 10 ILD2 0 When DMD = 0 9 ILD1 0 8 ILD0 0 Interrupt sensitivity Interrupt number 13 (INT8) priority level 000: Interrupt disabled 001-111: 1-7 When DMD = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIMC1 0 00: Low level 01: High level 10: Falling edge 11: Rising edge 4 EIMC0 0 3 DMC R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 12 as DMA trigger 2 ILC2 0 When DMC = 0 1 ILC1 0 0 ILC0 0 Interrupt sensitivity Interrupt number 12 (INT7) priority level 000: Interrupt disabled 001-111: 1-7 When DMC = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-51 2006-02-21 TMP1962C10BXBG 31 IMC4 (0xFFFF_E010) Bit Symbol Read/Write Reset Value Function 30 29 EIM131 0 28 EIM130 0 27 DM13 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 19 as DMA trigger 26 IL132 0 25 IL131 0 24 IL130 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM13 = 0 Interrupt number 19 (INTTX1) priority level 000: Interrupt disabled 001-111: 1-7 When DM13 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM121 0 20 EIM120 0 19 DM12 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 18 as DMA trigger 18 IL122 0 17 IL121 0 16 IL120 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM12 = 0 Interrupt number 18 (INTRX1) priority level 000: Interrupt disabled 001-111: 1-7 When DM12 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM111 0 12 EIM110 0 11 DM11 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 17 as DMA trigger 10 IL112 0 When DM11 = 0 9 IL111 0 8 IL110 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 17 (INTTX0) priority level 000: Interrupt disabled 001-111: 1-7 When DM11 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM101 0 4 EIM100 0 3 DM10 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 16 as DMA trigger 2 IL102 0 When DM10 = 0 1 IL101 0 0 IL100 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 16 (INTRX0) priority level 000: Interrupt disabled 001-111: 1-7 When DM10 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-52 2006-02-21 TMP1962C10BXBG 31 IMC5 (0xFFFF_E014) Bit Symbol Read/Write Reset Value Function 30 29 EIM171 0 28 EIM170 0 27 DM17 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 23 as DMA trigger 26 IL172 0 25 IL171 0 24 IL170 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM17 = 0 Interrupt number 23 (INTADHP) priority level 000: Interrupt disabled 001-111: 1-7 When DM17 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM161 0 20 EIM160 0 19 DM16 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 22 as DMA trigger 18 IL162 0 17 IL161 0 16 IL160 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM16 = 0 Interrupt number 22 (INTTX2) priority level 000: Interrupt disabled 001-111: 1-7 When DM16 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM151 0 12 EIM150 0 11 DM15 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 21 as DMA trigger 10 IL152 0 When DM15 = 0 9 IL151 0 8 IL150 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 21 (INTRX2) priority level 000: Interrupt disabled 001-111: 1-7 When DM15 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM141 0 4 EIM140 0 3 DM14 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 20 as DMA trigger 2 IL142 0 When DM14 = 0 1 IL141 0 0 IL140 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 20 (INTS0) priority level 000: Interrupt disabled 001-111: 1-7 When DM14 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-53 2006-02-21 TMP1962C10BXBG 31 IMC6 (0xFFFF_E018) Bit Symbol Read/Write Reset Value Function 30 29 EIM1B1 0 28 EIM1B0 0 27 DM1B R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 27 as DMA trigger 26 IL1B2 0 25 IL1B1 0 24 IL1B0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM1B = 0 Interrupt number 27 (INTTAG2) priority level 000: Interrupt disabled 001-111: 1-7 When DM1B = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM1A1 0 20 EIM1A0 0 19 DM1A R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 26 as DMA trigger 18 IL1A2 0 17 IL1A1 0 16 IL1A0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM1A = 0 Interrupt number 26 (INTTAG1) priority level 000: Interrupt disabled 001-111: 1-7 When DM1A = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM191 0 12 EIM190 0 11 DM19 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 25 as DMA trigger 10 IL192 0 When DM19 = 0 9 IL191 0 8 IL190 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 25 (INTTAG0) priority level 000: Interrupt disabled 001-111: 1-7 When DM19 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM181 0 4 EIM180 0 3 DM18 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 24 as DMA trigger 2 IL182 0 When DM18 = 0 1 IL181 0 0 IL180 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 24 (INTADM) priority level 000: Interrupt disabled 001-111: 1-7 When DM18 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-54 2006-02-21 TMP1962C10BXBG 31 IMC7 (0xFFFF_E01C) Bit Symbol Read/Write Reset Value Function 30 29 EIM1F1 0 28 EIM1F0 0 27 DM1F R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 31 as DMA trigger 26 IL1F2 0 25 IL1F1 0 24 IL1F0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM1F = 0 Interrupt number 31 (INTRX3) priority level 000: Interrupt disabled 001-111: 1-7 When DM1F = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM1E1 0 20 EIM1E0 0 19 DM1E R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 30 as DMA trigger 18 IL1E2 0 17 IL1E1 0 16 IL1E0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM1E = 0 Interrupt number 30 (INTTB1) priority level 000: Interrupt disabled 001-111: 1-7 When DM1E = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM1D1 0 12 EIM1D0 0 11 DM1D R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 29 as DMA trigger 10 IL1D2 0 When DM1D = 0 9 IL1D1 0 8 IL1D0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 29 (INTTB0) priority level 000: Interrupt disabled 001-111: 1-7 When DM1D = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM1C1 0 4 EIM1C0 0 3 DM1C R/W 0 Must be set to 0. 2 IL1C2 0 1 IL1C1 0 0 IL1C0 0 Must be set to 00. Must be set to 000. TMP1962-55 2006-02-21 TMP1962C10BXBG 31 IMC8 (0xFFFF_E020) Bit Symbol Read/Write Reset Value Function 30 29 EIM231 0 28 EIM230 0 27 DM23 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 35 as DMA trigger 26 IL232 0 25 IL231 0 24 IL230 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM23 = 0 Interrupt number 35 (INTRX5) priority level 000: Interrupt disabled 001-111: 1-7 When DM23 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM221 0 20 EIM220 0 19 DM22 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 34 as DMA trigger 18 IL222 0 17 IL221 0 16 IL220 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM22 = 0 Interrupt number 34 (INTTX4) priority level 000: Interrupt disabled 001-111: 1-7 When DM22 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM211 0 12 EIM210 0 11 DM21 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 33 as DMA trigger 10 IL212 0 When DM21 = 0 9 IL211 0 8 IL210 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 33 (INTRX4) priority level 000: Interrupt disabled 001-111: 1-7 When DM21 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM201 0 4 EIM200 0 3 DM20 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 32 as DMA trigger 2 IL202 0 When DM20 = 0 1 IL201 0 0 IL200 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 32 (INTTX3) priority level 000: Interrupt disabled 001-111: 1-7 When DM20 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-56 2006-02-21 TMP1962C10BXBG 31 IMC9 (0xFFFF_E024) Bit Symbol Read/Write Reset Value Function 30 29 EIM271 0 28 EIM270 0 27 DM27 R/W 0 Must be set to 0. 26 IL272 0 25 IL271 0 24 IL270 0 Must be set to 00. Must be set to 000. 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM261 0 20 EIM260 0 19 DM26 R/W 0 Must be set to 0. 18 IL262 0 17 IL261 0 16 IL260 0 Must be set to 00. Must be set to 000. 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM251 0 12 EIM250 0 11 DM25 R/W 0 Must be set to 0. 10 IL252 0 9 IL251 0 8 IL250 0 Must be set to 00. Must be set to 000. 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM241 0 4 EIM240 0 3 DM24 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 36 as DMA trigger 2 IL242 0 When DM24 = 0 1 IL241 0 0 IL240 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 36 (INTTX5) priority level 000: Interrupt disabled 001-111: 1-7 When DM24 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-57 2006-02-21 TMP1962C10BXBG 31 IMCA (0xFFFF_E028) Bit Symbol Read/Write Reset Value Function 30 29 EIM2B1 0 28 EIM2B0 0 27 DM2B R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 43 as DMA trigger 26 IL2B2 0 25 IL2B1 0 24 IL2B0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM2B = 0 Interrupt number 43 (INTCMP0) priority level 000: Interrupt disabled 001-111: 1-7 When DM2B = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM2A1 0 20 EIM2A0 0 19 DM2A R/W 0 Must be set to 0. 18 IL2A2 0 17 IL2A1 0 16 IL2A0 0 Must be set to 00. Must be set to 000. 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM291 0 12 EIM290 0 11 DM29 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 41 as DMA trigger 10 IL292 0 When DM29 = 0 9 IL291 0 8 IL290 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 41 (INTCAPG1) priority level 000: Interrupt disabled 001-111: 1-7 When DM29 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM281 0 4 EIM280 0 3 DM28 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 40 as DMA trigger 2 IL282 0 When DM28 = 0 1 IL281 0 0 IL280 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 40 (INTCAPG0) priority level 000: Interrupt disabled 001-111: 1-7 When DM28 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-58 2006-02-21 TMP1962C10BXBG 31 IMCB (0xFFFF_E02C) Bit Symbol Read/Write Reset Value Function 30 29 EIM2F1 0 28 EIM2F0 0 27 DM2F R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 47 as DMA trigger 26 IL2F2 0 25 IL2F1 0 24 IL2F0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM2F = 0 Interrupt number 47 (INTCMP4) priority level 000: Interrupt disabled 001-111: 1-7 When DM2F = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM2E1 0 20 EIM2E0 0 19 DM2E R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 46 as DMA trigger 18 IL2E2 0 17 IL2E1 0 16 IL2E0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM2E = 0 Interrupt number 46 (INTCMP3) priority level 000: Interrupt disabled 001-111: 1-7 When DM2E = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM2D1 0 12 EIM2D0 0 11 DM2D R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 45 as DMA trigger 10 IL2D2 0 When DM2D = 0 9 IL2D1 0 8 IL2D0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 45 (INTCMP2) priority level 000: Interrupt disabled 001-111: 1-7 When DM2D = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM2C1 0 4 EIM2C0 0 3 DM2C R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 44 as DMA trigger 2 IL2C2 0 When DM2C = 0 1 IL2C1 0 0 IL2C0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 44 (INTCMP1) priority level 000: Interrupt disabled 001-111: 1-7 When DM2C = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-59 2006-02-21 TMP1962C10BXBG 31 IMCC (0xFFFF_E030) Bit Symbol Read/Write Reset Value Function 30 29 EIM331 0 28 EIM330 0 27 DM33 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 51 as DMA trigger 26 IL332 0 25 IL331 0 24 IL330 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. When DM33 = 0 Interrupt number 51 (INTCMP6) priority level 000: Interrupt disabled 001-111: 1-7 When DM33 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM321 0 20 EIM320 0 19 DM32 R/W 0 DMA trigger 0: Disable 18 IL322 0 17 IL321 0 16 IL320 0 Interrupt sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited When DM32 = 0 Interrupt number 50 (INTTB3) priority level 000: Interrupt disabled 001-111: 1-7 When DM32 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 1: Enable interrupt 11: Rising edge number Must be set to 01 when 50 as used for STOP DMA wake-up signaling; trigger otherwise, must be set to 11. 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM311 0 12 EIM310 0 11 DM31 R/W 0 DMA trigger 0: Disable 10 IL312 0 When DM31 = 0 9 IL311 0 8 IL310 0 Interrupt sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited 11: Rising edge Interrupt number 49 (INTTB2) priority level 000: Interrupt disabled 001-111: 1-7 When DM31 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 1: Enable interrupt number Must be set to 01 when 49 as used for STOP DMA wake-up signaling; trigger otherwise, must be set to 11. 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM301 0 4 EIM300 0 3 DM30 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 48 as DMA trigger 2 IL302 0 When DM30 = 0 1 IL301 0 0 IL300 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 48 (INTCMP5) priority level 000: Interrupt disabled 001-111: 1-7 When DM30 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-60 2006-02-21 TMP1962C10BXBG 31 IMCD (0xFFFF_E034) Bit Symbol Read/Write Reset Value Function 0 0 0 DMA trigger 0: Disable 1: Enable interrupt number 55 as DMA trigger Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Rising edge Must be set to 10. 30 29 EIM371 28 EIM370 27 DM37 R/W 26 IL372 0 25 IL371 0 24 IL370 0 When DM37 = 0 Interrupt number 55 (INTDMA1) priority level 000: Interrupt disabled 001-111: 1-7 When DM37 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM361 0 20 EIM360 0 19 DM36 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 54 as DMA trigger 18 IL362 0 17 IL361 0 16 IL360 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Rising edge Must be set to 10. When DM36 = 0 Interrupt number 54 (INTDMA0) priority level 000: Interrupt disabled 001-111: 1-7 When DM36 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM351 0 12 EIM350 0 11 DM35 R/W 0 Must be set to 0. 10 IL352 0 9 IL351 0 8 IL350 0 Must be set to 00. Must be set to 000. 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM341 0 4 EIM340 0 3 DM34 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 52 as DMA trigger 2 IL342 0 When DM34 = 0 1 IL341 0 0 IL340 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. Interrupt number 52 (INTCMP7) priority level 000: Interrupt disabled 001-111: 1-7 When DM34 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-61 2006-02-21 TMP1962C10BXBG 31 IMCE (0xFFFF_E038) Bit Symbol Read/Write Reset Value Function 0 0 0 DMA trigger 0: Disable 1: Enable interrupt number 59 as DMA trigger Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Setting prohibited 11: Rising edge Must be set to 11. 30 29 EIM3B1 28 EIM3B0 27 DM3B R/W 26 IL3B2 0 25 IL3B1 0 24 IL3B0 0 When DM3B = 0 Interrupt number 59 (INTAD) priority level 000: Interrupt disabled 001-111: 1-7 When DM3B = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM3A1 0 20 EIM3A0 0 19 DM3A R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 58 as DMA trigger 18 IL3A2 0 17 IL3A1 0 16 IL3A0 0 Interrupt sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited 11: Setting prohibited Must be set to 01. When DM3A = 0 Interrupt number 58 (INTRTC) priority level 000: Interrupt disabled 001-111: 1-7 When DM3A = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM391 0 12 EIM390 0 11 DM39 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 57 as DMA trigger 10 IL392 0 When DM39 = 0 9 IL391 0 8 IL390 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. Interrupt number 57 (INTDMA3) priority level 000: Interrupt disabled 001-111: 1-7 When DM39 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM381 0 4 EIM380 0 3 DM38 R/W 0 DMA trigger 0: Disable 1: Enable interrupt number 56 as DMA trigger 2 IL382 0 When DM38 = 0 1 IL381 0 0 IL380 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. Interrupt number 56 (INTDMA2) priority level 000: Interrupt disabled 001-111: 1-7 When DM38 = 1 DMAC channel select 000-011: 0-3 100-111: 4-7 TMP1962-62 2006-02-21 TMP1962C10BXBG 31 IMCF (0xFFFF_E03C) Bit Symbol Read/Write Reset Value Function 30 29 EIM3F1 0 28 EIM3F0 0 27 DM3F R/W 0 DMA trigger 26 IL3F2 0 25 IL3F1 0 24 IL3F0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. When DM3F = 0 Interrupt number 63 (INTDMA7) 0: Disable priority level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM3F = 1 63 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 23 Bit Symbol Read/Write Reset Value Function 22 21 EIM3E1 0 20 EIM3E0 0 19 DM3E R/W 0 DMA trigger 18 IL3E2 0 17 IL3E1 0 16 IL3E0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. When DM3E = 0 Interrupt number 62 (INTDMA6) 0: Disable priority level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM3E = 1 62 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 15 Bit Symbol Read/Write Reset Value Function 14 13 EIM3D1 0 12 EIM3D0 0 11 DM3D R/W 0 DMA trigger 10 IL3D2 0 9 IL3D1 0 8 IL3D0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. When DM3D = 0 Interrupt number 61 (INTDMA5) 0: Disable priority level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM3D = 1 61 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 7 Bit Symbol Read/Write Reset Value Function 6 5 EIM3C1 0 4 EIM3C0 0 3 DM3C R/W 0 2 IL3C2 0 1 IL3C1 0 0 IL3C0 0 Interrupt sensitivity 00: Setting prohibited 01: Setting prohibited 10: Falling edge 11: Setting prohibited Must be set to 10. When DM3C = 0 DMA trigger Interrupt number 60 (INTDMA4) 0: Disable priority level 1: Enable 000: Interrupt disabled interrupt 001-111: 1-7 number When DM3C = 1 60 as DMAC channel select DMA 000-011: 0-3 trigger 100-111: 4-7 Note 1: Interrupt sensitivity must be programmed when interrupts are enabled. Note 2 When an interrupt is used to trigger a DMAC channel, that DMAC channel must be put in Ready state after the programming of the INTC. TMP1962-63 2006-02-21 TMP1962C10BXBG 6.4.3 Interrupt Request Clear Register Loading the EICLR[5:0] field of this register with the IVR[9:4] value of the IVR causes the corresponding interrupt to be cleared. 31 INTCLR (0xFFFF_E060) Bit Symbol Read/Write Reset Value Function 30 29 28 27 26 25 24 23 Bit Symbol Read/Write Reset Value Function 22 21 20 19 18 17 16 15 Bit Symbol Read/Write Reset Value Function 14 13 12 11 10 9 8 7 Bit Symbol Read/Write Reset Value Function 6 5 EICLR5 4 EICLR4 3 EICLR3 W 2 EICLR2 1 EICLR1 0 EICLR0 IVRL[9:4] value for an interrupt to be cleared Note 1: An interrupt request must not be cleared before the TX19 core processor reads the IVR value. Note 2: Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC). 1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of the Status register. 2. Disable the desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register. 3. Execute the SYNC instruction. 4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the Status register. Example: mtc0 sb sync mtc0 r0, r0, $sp, r31 ; _DI () ; ; _SYNC () ; ; _EI () ; IMC** ; IMC** = 0 ; r31 TMP1962-64 2006-02-21 TMP1962C10BXBG 6.4.4 INTCG Registers (STOP Wake-up Signaling) STOP Wake-up Signaling 31 IMCGA0 (0xFFFF_EE10) Bit Symbol Read/Write Reset Value Function 1 30 29 EMCG31 R/W 28 EMCG30 0 27 26 25 24 INT3EN R/W 0 INT3 for standby wake-up signaling 0: Disable 1: Enable INT3 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 23 Bit Symbol Read/Write Reset Value Function 22 21 EMCG21 1 R/W 20 EMCG20 0 19 18 17 16 INT2EN R/W 0 INT2 for standby wake-up signaling 0: Disable 1: Enable INT2 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 Bit Symbol Read/Write Reset Value Function 14 13 EMCG11 1 R/W 12 EMCG10 0 11 10 9 8 INT1EN R/W 0 INT1 for standby wake-up signaling 0: Disable 1: Enable INT1 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 7 Bit Symbol Read/Write Reset Value Function 6 5 EMCG01 1 R/W 4 EMCG00 0 3 2 1 0 INT0EN R/W 0 INT0 for standby wake-up signaling 0: Disable 1: Enable INT0 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge TMP1962-65 2006-02-21 TMP1962C10BXBG 31 IMCGB0 (0xFFFF_EE14) Bit Symbol Read/Write Reset Value Function 30 29 R/W 1 28 27 26 25 24 R/W 1 0 Must be set to 0. 23 Bit Symbol Read/Write Reset Value Function 22 21 R/W 1 20 19 18 17 16 R/W 0 0 Must be set to 0. 15 Bit Symbol Read/Write Reset Value Function 14 13 EMCG51 0 R/W 12 EMCG50 1 11 10 9 8 KWUPEN R/W 0 KWUP for standby wake-up signaling 0: Disable 1: Enable KWUP standby wake-up interrupt sensitivity 00: Setting prohibited 01: High level 10: Setting prohibited 11: Setting prohibited Must be set to 01. 7 Bit Symbol Read/Write Reset Value Function 6 5 EMCG41 1 R/W 4 EMCG40 0 3 2 1 0 INT4EN R/W 0 INT4 for standby wake-up signaling 0: Disable 1: Enable INT4 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge TMP1962-66 2006-02-21 TMP1962C10BXBG 31 IMCGC0 (0xFFFF_EE18) Bit Symbol Read/Write Reset Value Function 30 29 EMCGB1 1 R/W 28 EMCGB0 0 27 26 25 24 INT6EN R/W 0 INT6 for standby wake-up signaling 0: Disable 1: Enable INT6 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 23 Bit Symbol Read/Write Reset Value Function 22 21 EMCGA1 1 R/W 20 EMCGA0 0 19 18 17 16 INT5EN R/W 0 INT5 for standby wake-up signaling 0: Disable 1: Enable INT5 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 Bit Symbol Read/Write Reset Value Function 14 13 R/W 1 12 11 10 9 8 R/W 1 0 Must be set to 0. 7 Bit Symbol Read/Write Reset Value Function 6 5 R/W 1 4 3 2 1 0 R/W 1 0 Must be set to 0. TMP1962-67 2006-02-21 TMP1962C10BXBG 31 IMCGD0 (0xFFFF_EE1C) Bit Symbol Read/Write Reset Value Function 30 29 EMCGF1 1 R/W 28 EMCGF0 0 27 26 25 24 INTAEN R/W 0 INTA for standby wake-up signaling 0: Disable 1: Enable INTA standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 23 Bit Symbol Read/Write Reset Value Function 22 21 EMCGE1 1 R/W 20 EMCGE0 0 19 18 17 16 INT9EN R/W 0 INT9 for standby wake-up signaling 0: Disable 1: Enable INT9 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 Bit Symbol Read/Write Reset Value Function 14 13 EMCGD1 1 R/W 12 EMCGD0 0 11 10 9 8 INT8EN R/W 0 INT8 for standby wake-up signaling 0: Disable 1: Enable INT8 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 7 Bit Symbol Read/Write Reset Value Function 6 5 EMCGC1 1 R/W 4 EMCGC0 0 3 2 1 0 INT7EN R/W 0 INT7 for standby wake-up signaling 0: Disable 1: Enable INT7 standby wake-up interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge TMP1962-68 2006-02-21 TMP1962C10BXBG Note 1: Interrupt sensitivity must be programmed when interrupts are enabled for STOP wake-up signaling. Note 2: Follow the steps below to use an interrupt. 1. Enable the corresponding pin as an interrupt source if it is also used as a general-purpose port pin or has other functions. 2. Specify the interrupt sensitivity during initialization. 3. Clear any corresponding interrupt request. 4. Enable the interrupt source. Note 3: The interrupt sensitivity and other settings must be programmed when the interrupt is disabled. Note 4: The TMP1962 supports the use of 15 interrupt sources for STOP wake-up signaling: INT0-INTA, INTRTC, INTTB2/INTTB3 and KWUP0-KWUPD. For INT0-INTA, the CG block controls whether these interrupt sources are enabled as wake-up signal sources and defines the interrupt sensitivity. For KWUP0-KWUPD, the CG block controls whether these interrupt sources are enabled as wake-up signal sources while the KWUPSTx defines the interrupt sensitivity. For the above 15 interrupt sources, the interrupt sensitivity field in the INTC has no effect, but it must be set to "high-level." Example: Enabling the INT0 interrupt IMCGA0 Interrupts other than those used for STOP wake-up signaling are programmed in the INTC block. Note 5: When INT0-INTA are used as general-purpose interrupts, the INTC defines the interrupt sensitivity; the CG need not be programmed. When KWUP0-KWUPD are used as general-purpose interrupts, the KWUPSTn register defines the interrupt sensitivity; the CG need not be programmed, but the interrupt sensitivity field in the INTC must be set to "high-level." INTRTC requires settings in both the CG and INTC even when it is used as a general-purpose interrupt. Interrupts other than those used for STOP wake-up signaling are programmed in the INTC block. TMP1962-69 2006-02-21 TMP1962C10BXBG 31 EICRCG (0xFFFF_EE20) Bit Symbol Read/Write Reset Value Function 30 29 28 27 26 25 24 23 Bit Symbol Read/Write Reset Value Function 22 21 20 15 Bit Symbol Read/Write Reset Value Function 14 13 12 7 Bit Symbol Read/Write Reset Value Function 6 5 4 3 ICRCG3 0000: INT0 0001: INT1 0010: INT2 0011: INT3 0100: INT4 2 ICRCG2 W 0101: KWUP 1 ICRCG1 0 ICRCG0 Clear the corresponding interrupt request. 1010: INT5 0110: reserved 1011: INT6 0111: reserved 1100: INT7 1000: reserved 1101: INT8 1001: reserved 1110: INT9 1111: INTA Note 6: To clear interrupts used for STOP wake-up signaling, program the following registers: 1. For KWUP, program the KWUPCLR. 2. For INT0-INTA, INTTB2, INTTB3, and INTRTC, program both the EICRCG register in the CG block, shown above, and the INTCLR register in the INTC block. 3. For other interrupt sources, program the INTCRL register in the INTC block. TMP1962-70 2006-02-21 TMP1962C10BXBG 7. 7.1 I/O Ports Port 0 (P00 - P07) Eight Port 0 pins can be individually programmed to function as discrete general-purpose I/O pins, the D[0:7] bits of the data bus, or the AD[0:7] bits of the address/data bus. The P0CR register controls the direction of the Port 0 pins. Upon reset, the P0CR register bits are cleared, configuring all Port 0 pins as inputs. During external memory accesses, Port 0 pins are automatically configured as D[0:7] or AD[0:7], with the P0CR register bits all cleared. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected (D[0:7]). If the BUSMD pin is driven high upon reset, Multiplexed Bus mode is selected (AD[0:7]). Reset Direction Control (bitwise) STOP DRIVE P0CR Write Internal Data Bus Output Latch Output Buffer Port 0 P00 - P07 (D0 - D7) (AD0 - AD7) P0 Write P0 Read Figure 7.1 Port 0 (P00 - P07) Note: The above diagram does not depict the address/data bus function. TMP1962-71 2006-02-21 TMP1962C10BXBG Port 0 Register 7 P0 (0xFFFF_F003) Bit Symbol Read/Write Reset Value P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Input mode (The output latch is cleared to 0.) Port 0 Control Register 7 P0CR (0xFFFF_F001) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P07C 6 P06C 5 P05C 4 P04C W 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: In, 1: Out (Functions as D7-D0 or AD7-AD0 during external memory accesses, with all bits cleared.) Figure 7.2 Port 0 Registers TMP1962-72 2006-02-21 TMP1962C10BXBG 7.2 Port 1 (P10 - P17) Eight Port 1 pins can be individually programmed to function as discrete general-purpose I/O pins, the D[8:15] bits of the data bus, the AD[8:15] bits of the address/data bus, or the A[8:15] bits of the address bus. The P1CR and P1FC registers select the direction and function of the Port 1 pins. Upon reset, the output latch (P1) bits are cleared to all 0s, and the P1CR and P1FC register bits are cleared to all 0s, configuring all Port 1 pins as input port pins. For external memory accesses, Port 1 pins must be configured as the address bus or address/data bus through the programming of the P1CR and P1FC. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected (D[8:15]). If the BUSMD pin is driven high upon reset, Multiplexed Bus mode is selected (AD[8:15] or A[8:15]). Reset Direction Control (bitwise) P1CR Write Function Control (bitwise) Internal Data Bus P1FC Write STOP DRIVE Port 1 P10 - P17 (D8 - D15) (AD8 - AD15/A8 - A15) Output Latch Output Buffer P1 Write P1 Read Figure 7.3 Port 1 (P10 - P17) Note: The above diagram does not depict the address/data bus function. TMP1962-73 2006-02-21 TMP1962C10BXBG Port 1 Register 7 P1 (0xFFFF_F002) Bit Symbol Read/Write Reset Value P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Input mode (The output latch is cleared to 0.) Port 1 Control Register 7 P1CR (0xFFFF_F007) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Refer to P1FC. Port 1 Function Register 7 P1FC (0xFFFF_F006) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P17F 6 P16F 5 P15F 4 P14F W 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input port, 01: Output port, 10: D15-D8 or AD15-AD8, 11: A15-A8 Port 1 Function Settings P1CR Figure 7.4 Port 1 Registers TMP1962-74 2006-02-21 TMP1962C10BXBG 7.3 Port 2 (P20 - P27) Eight Port 2 pins can be individually programmed to function as discrete general-purpose I/O pins, the A[0:7] bits of the address bus, or the A[16:23] bits of the address bus. The P2CR and P2FC registers select the direction and function of the Port 2 pins. Upon reset, the output latch (P2) bits are cleared to all 0s, and the P2CR and P2FC register bits are cleared to all 0s, configuring all Port 2 pins as input port pins. For external memory accesses, Port 2 pins must be configured as the address bus through the programming of the P2CR and P2FC. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected (A[16:23]). If the BUSMD pin is driven high upon reset, Multiplexed Bus mode is selected (A[0:7] or A[16:23]). A16 - A23 A0 - A7 Reset Selector S B A Y Direction Control (bitwise) P2CR Write Function Control (bitwise) STOP DRIVE S B Selector Output Latch A Y Output Buffer P2 Write Port 2 P20 - P27 (A16 - A23) (A0-A7/A16 - A23) Internal Data Bus P2FC Write P2 Read Figure 7.5 Port 2 (P20 - P27) TMP1962-75 2006-02-21 TMP1962C10BXBG Port 2 Register 7 P2 (0xFFFF_F011) Bit Symbol Read/Write Reset Value P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Input mode (The output latch is cleared to 0.) Port 2 Control Register 7 P2CR (0xFFFF_F017) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 Refer to P2FC. Port 2 Function Register 7 P2FC (0xFFFF_F016) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P27F 6 P26F 5 P25F 4 P24F W 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input port, 01: Output port, 10: A7-A0, 11: A23-A16 Port 2 Function Settings P2CR Figure 7.6 Port 2 Registers TMP1962-76 2006-02-21 TMP1962C10BXBG 7.4 Port 3 (P30 - P37) Eight Port 3 pins can be individually programmed to function as either discrete general-purpose I/O pins or CPU control/status pins. In either case, P30 and P31 are output-only pins. The P3CR and P3FC registers select the direction and function of the Port 3 pins. Upon reset, the P30 and P31 output latch bits are set to 1 and the P32-P36 output latch bits are set to 1 if the RSTPUP pin is high, or cleared to 0 if the RSTPUP pin is low. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected, causing the P37 output latch bit to be set to 1. If the BUSMD pin is driven high upon reset, Multiplexed Bus mode is selected, causing the P37 output latch bit to be cleared to 0. Bits 2 to 6 of the P3CR are cleared to 0 upon reset (bits 0 and 1 are not used). Bit 7 of the P3CR is cleared to 0 in Separate Bus mode, or set to 1 in Multiplexed Bus mode. All bits of the P3FC register are cleared upon reset, configuring P30 and P31 as output port pins (high), P32-P36 as input port pins with pull-up enabled (if the RSTPUP is high) or disabled (if the RSTPUP is low), and P37 as an input port pin (in Separate Bus mode) or output port pin (in Multiplexed Bus mode). When P30 is configured as RD (P3FC.P30F = 1), the Read Strobe signal is activated when external address space is accessed. Likewise, when P31 is configured as WR (P3FC.P31F = 1), the Write Strobe signal is activated when external address space is accessed. While BUSAK is asserted, the internal pull-up resistors for P32 and P36 are enabled, if the P3FC.P3xF bit is set to 1. Reset Function Control (bitwise) Internal Data Bus P3FC Write A B Selector S Output Latch S Output Buffer P30 ( RD ) P31 ( WR ) P3 Write RD , WR P3 Read Figure 7.7 Port 3 (P30, P31) TMP1962-77 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) P3CR Write STOP DRIVE Function Control (bitwise) Internal Data Bus P3FC Write RSTPUP S SR Output Latch A B Reset P3 Write HWR , BUSAK , R / W P-ch Programmable Pull-up Resistor Selector Output Buffer P32 ( HWR ) P35 ( BUSAK ) P36 ( R / W ) P3 Read Figure 7.8 Port 3 (P32, P35, P36) TMP1962-78 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) STOP DRIVE P3CR Write RSTPUP Internal Data Bus P-ch Programmable Pull-up Resistor SR Output Latch Output Buffer P3 Write Reset P33 ( WAIT / RDY ) Internal WAIT / RDY P3 Read Reset Direction Control (bitwise) STOP DRIVE P3CR Write Function Control (bitwise) Internal Data Bus P3CR Write P-ch RSTPUP Programmable Pull-up Resistor SR Output Latch Output Buffer P3 Write Reset P34 ( BUSRQ ) P3 Read Internal BUSRQ Figure 7.9 Port 3 (P33, P34) TMP1962-79 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) P3CR Write STOP DRIVE Function Control (bitwise) Internal Data Bus P3FC Write BUSMD S SR Output Latch A B Reset P3 Write ALE Selector P37 (ALE) Output Buffer P3 Read Figure 7.10 Port 3 (P37) TMP1962-80 2006-02-21 TMP1962C10BXBG Port 3 Register 7 P3 (0xFFFF_F01B) Bit Symbol Read/Write Reset Value P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 0 P30 Depends Input mode RSTPUP = 1 on the bus 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) mode. 0 0 0 0 0 RSTPUP = 0 Output mode 1 1 Port 3 Control Register 7 P3CR (0xFFFF_F019) Bit Symbol Read/Write Reset Value Function Depends on the bus mode. 0 0 P37C 6 P36C 5 P35C W 4 P34C 0 3 P33C 0 0: Input, 1: Output 2 P32C 0 1 0 Port 3 Function Register 7 P3FC (0xFFFF_F018) Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: ALE 0 0: PORT 1: R / W 0 0: PORT 1: BUSAK 6 P36F 5 P35F 4 P34F W 0 0: PORT 1: BUSRQ 3 P33F 0 0: PORT/ WAIT 1: PORT/ RDY 2 P32F 0 0: PORT 1: HWR 1 P31F 0 0: PORT 1: WR 0 P30F 0 0: PORT 1: RD P37F BUSRQ Settings P30 ( RD ) Function Settings 1 0 P3FC BUSAK Settings P3FC R / W Settings 1 1 1 Assert RD only during external accesses. P31 ( WR ) Function Settings 1 1 P3FC P3FC 1 Assert WR only during external accesses. HWR Settings P3FC WAIT / RDY Settings 1 1 Separate Bus mode: Upon reset, configured as input port Multiplexed Bus mode: Upon reset, configured as output port (Outputs a 0.) WAIT 1 RDY Figure 7.11 Port 3 Registers TMP1962-81 2006-02-21 TMP1962C10BXBG 7.5 Port 4 (P40 - P44) P40-P43 can be individually programmed to function as either discrete general-purpose I/O pins or programmable chip select ( CS0 - CS3 ) pins. P44 can be programmed to function as either a general-purpose I/O pin or a system clock output (SCOUT) pin. The P4CR and P4FC registers select the direction and function of the Port 4 pins. Upon reset, the P40-P43 output latch bits are set to 1 if the RSTPUP pin is high, or cleared to 0 if the RSTPUP pin is low. The P44 output latch bit is set to 1 regardless of the state of the RSTPUP pin. The P4CR and P4FC register bits are cleared upon reset, configuring P40-P43 as input port pins with pull-up enabled (if the RSTPUP is high) or disabled (if the RSTPUP is low), and P44 as an input port pin with pull-up disabled (regardless of the state of the RSTPUP pin). Reset Direction Control (bitwise) P4CR Write STOP DRIVE Function Control (bitwise) Internal Data Bus P4FC Write RSTPUP S SR Output Latch A B Reset P4 Write CS0 , CS1 , CS2 , CS3 P-ch Programmable Pull-up Resistor P40 ( CS0 ) P41 ( CS1 ) P42 ( CS2 ) P43 ( CS3 ) Selector Output Buffer P4 Read Figure 7.12 Port 4 (P40 - P43) TMP1962-82 2006-02-21 TMP1962C10BXBG Reset R Direction Control (bitwise) STOP DRIVE P4CR Write R Function Control (bitwise) Internal Data Bus P4FC Write S Output Latch AS Selector Y P44 (SCOUT) Reset P4 Write B S B Y Selector P4 Read A fsys Clock fsys/2 Clock SYSCR3 Figure 7.13 Port 4 (P44) TMP1962-83 2006-02-21 TMP1962C10BXBG Port 4 Register 7 P4 (0xFFFF_F01D) Bit Symbol Read/Write Reset Value RSTPUP=1 RSTPUP=0 1 1 0 6 5 4 P44 3 P43 2 P42 R/W Input mode 1 P41 0 P40 1 (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) 0 0 0 Port 4 Control Register 7 P4CR (0xFFFF_F023) Bit Symbol Read/Write Reset Value 0 0 6 5 4 P44C 3 P43C 2 P42C W 0 0: Input, 1: Output 1 P41C 0 0 P40C 0 Port 4 Function Register 7 P4FC (0xFFFF_F022) Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: SCOUT 0 6 5 4 P44F 3 P43F 2 P42F W 0 0: PORT 1: CS 1 P41F 0 0 P40F 0 0 1 0 1 0 1 0 1 PORT (P40) CS0 PORT (P41) CS1 PORT (P42) CS2 PORT (P43) CS3 Figure 7.14 Port 4 Registers TMP1962-84 2006-02-21 TMP1962C10BXBG 7.6 Port 5 (P50 - P57) Eight Port 5 pins can be individually programmed to function as discrete general-purpose I/O pins or the A[0:7] bits of the address bus. The P5CR and P5FC registers select the direction and function of the Port 5 pins. Upon reset, the output latch (P5) bits are set to all 1s, and the P5CR and P5FC register bits are cleared to all 0s, configuring all Port 5 pins as input port pins. For external memory accesses, Port 5 pins must be configured as the address bus through the programming of the P5CR and P5FC. Note that Port 5 pins can be used as address bus bits in Separate Bus mode only. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected. Reset A0 - A7 Direction Control (bitwise) P5CR Write Function Control (bitwise) STOP DRIVE S Selector B Output Latch A Internal Data Bus P5FC Write Y Output Buffer Port 5 P50 - P57 (A0 - A7) P5 Write P5 Read Figure 7.15 Port 5 (P50 - P57) TMP1962-85 2006-02-21 TMP1962C10BXBG Port 5 Register 7 P5 (0xFFFF_F02B) Bit Symbol Read/Write Reset Value P57 6 P56 5 P55 4 P54 R/W 3 P53 2 P52 1 P51 0 P50 Input mode (The output latch is set to 1.) Port 5 Control Register 7 P5CR (0xFFFF_F02F) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P57C 6 P56C 5 P55C 4 P54C W 3 P53C 0 2 P52C 0 1 P51C 0 0 P50C 0 Refer to P5FC. Port 5 Function Register 7 P5FC (0xFFFF_F02E) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P57F 6 P56F 5 P55F 4 P54F W 3 P53F 0 2 P52F 0 1 P51F 0 0 P50F 0 P5FC/P5CR = 00: Input port, 01: Output port, 10: Input port, 11: A7-A0 Port 5 Function Settings P5CR Figure 7.16 Port 5 Registers TMP1962-86 2006-02-21 TMP1962C10BXBG 7.7 Port 6 (P60 - P67) Eight Port 6 pins can be individually programmed to function as discrete general-purpose I/O pins or the A[8:15] bits of the address bus. The P6CR and P6FC registers select the direction and function of the Port 6 pins. Upon reset, the output latch (P6) bits are set to all 1s, and the P6CR and P6FC register bits are cleared to all 0s, configuring all Port 6 pins as input port pins. For external memory accesses, Port 6 pins must be configured as the address bus through the programming of the P6CR and P6FC. Note that Port 6 pins can be used as address bus bits in Separate Bus mode only. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected. Reset A8 - A15 Direction Control (bitwise) P6CR Write Function Control (bitwise) STOP DRIVE S B Selector Output Latch A Y Output Buffer P6 Write Port 6 P60 - P67 (A8 - A15) Internal Data Bus P6FC Write P6 Read Figure 7.17 Port 6 (P60 - P67) TMP1962-87 2006-02-21 TMP1962C10BXBG Port 6 Register 7 P6 (0xFFFF_F02A) Bit Symbol Read/Write Reset Value P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Input mode (The output latch is set to 1.) Port 6 Control Register 7 P6CR (0xFFFF_F02D) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 2 P62C 0 1 P61C 0 0 P60C 0 Refer to P6FC. Port 6 Function Register 7 P6FC (0xFFFF_F02C) Bit Symbol Read/Write Reset Value Function 0 0 0 0 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 0 2 P62F 0 1 P61F 0 0 P60F 0 P6FC/P6CR = 00: Input port, 01: Output port, 10: Input port, 11: A15-A8 Port 6 Function Settings P6CR Figure 7.18 Port 6 Registers TMP1962-88 2006-02-21 TMP1962C10BXBG 7.8 Port 7 (P70 - 77), Port 8 (P80 - 87) and Port 9 (P90 - 97) Port 7-9 pins are input-only pins shared with the analog input pins of the A/D Converter (ADC). Port 7 - 9 P70 - P97 (AN0 - AN23) Internal Data Bus Port 7 - 9 Read Reset A/D Conversion Result Register AD Read A/D Converter Channel Selector Figure 7.19 Port 7-9 (P70 - 77, P80 - 87, P90 - 97) TMP1962-89 2006-02-21 TMP1962C10BXBG Port 7 Register 7 P7 0xFFFF_F043 Bit Symbol Read/Write Reset Value P77 6 P76 5 P75 4 P74 R 3 P73 2 P72 1 P71 0 P70 Input mode Port 8 Register 7 P8 0xFFFF_F042 Bit Symbol Read/Write Reset Value P87 6 P86 5 P85 4 P84 R 3 P83 2 P82 1 P81 0 P80 Input mode Port 9 Register 7 P9 0xFFFF_F041 Bit Symbol Read/Write Reset Value P97 6 P96 5 P95 4 P94 R 3 P93 2 P92 1 P91 0 P90 Input mode Figure 7.20 Port 7 - 9 Registers TMP1962-90 2006-02-21 TMP1962C10BXBG 7.9 Port A (PA0 - PA7) Eight Port A pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PACR register selects the direction of the Port A pins. Upon reset, the PACR register bits are cleared to all 0s, configuring all Port A pins as input port pins. PA0 and PA2 can be programmed as inputs to 8-bit timers. PA1 and PA3-PA7 can be programmed as outputs from 8-bit timers. Setting the PAFC register bits configures the corresponding Port A pins for timer functions. A reset clears the PACR and PAFC register bits, configuring all Port A pins as input port pins. Reset Direction Control (bitwise) PACR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PAFC Write S Output Latch PA0 (TA0IN) PA2 (TA2IN) PA Write S Selector B PA Read TA0IN TA2IN A Figure 7.21 Port A (PA0, PA2) TMP1962-91 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PACR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PAFC Write S Output Latch A Selector Timer Flip-Flop Output PA Write B S PA1 (TA1OUT) PA3 (TA3OUT) PA4 (TA5OUT) PA5 (TA7OUT) PA6 (TA9OUT) PA7 (TABOUT) TA1OUT, TA7OUT TA3OUT, TA9OUT TA5OUT, TABOUT S B Selector PA Read A Figure 7.22 Port A (PA1, PA3, PA4, PA5, PA6, PA7) TMP1962-92 2006-02-21 TMP1962C10BXBG Port A Register 7 PA 0xFFFF_F040 Bit Symbol Read/Write Reset Value PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 Input mode (The output latch is set to 1.) Port A Control Register 7 PACR 0xFFFF_F044 Bit Symbol Read/Write Reset Value Function 0 PA7C 6 PA6C 0 5 PA5C 0 4 PA4C W 0 3 PA3C 0 2 PA2C 0 1 PA1C 0 0 PA0C 0 0: Input, 1: Output Port A Function Register 7 PAFC 0xFFFF_F048 Bit Symbol Read/Write Reset Value Function 0 0: PORT PA7F 6 PA6F 0 0: PORT 5 PA5F 0 0: PORT 4 PA4F W 0 0: PORT 3 PA3F 0 0: PORT 2 PA2F 0 0: PORT 1 PA1F 0 0: PORT 0 PA0F 0 0: PORT 1: TABOUT 1: TA9OUT 1: TA7OUT 1: TA5OUT 1: TA3OUT 1: TA2IN 1: TA1OUT 1: TA0IN Figure 7.23 Port A Registers TMP1962-93 2006-02-21 TMP1962C10BXBG 7.10 Port B (PB0 - PB7) Eight Port B pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PBCR register selects the direction of the Port B pins. Upon reset, the PBCR register bits are cleared to all 0s, configuring all Port B pins as input port pins. PB0, PB1, PB4 and PB7 can be programmed as outputs from 16-bit timers. PB2, PB3, PB5 and PB6 can be programmed as inputs to 16-bit timers or external interrupt request pins. Setting the PBFC register bits configures the corresponding Port B pins for dedicated functions. A reset clears the PBCR and PBFC register bits, configuring all Port B pins as input port pins. Reset Direction Control (bitwise) PBCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PBFC Write S Output Latch A Selector Timer Flip-Flop Output TB0OUT TB1OUT TB2OUT TB3OUT PB Read PB Write B S PB0 (TB0OUT) PB1 (TB1OUT) PB4 (TB2OUT) PB7 (TB3OUT) S B Selector A Figure 7.24 Port B (PB0, PB1, PB4, PB7) TMP1962-94 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PBCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PBFC Write S Output Latch PB2 (TB2IN0/INT5) PB3 (TB2IN1/INT6) PB5 (TB3IN0/INT7) PB6 (TB3IN1/INT8) S Selector PB Read TB2IN0, TB2IN1 TB3IN0, TB3IN1 INT5, 6, 7, 8 A B PB Write Figure 7.25 Port B (PB2, PB3, PB5, PB6) TMP1962-95 2006-02-21 TMP1962C10BXBG Port B Register 7 PB 0xFFFF_F053 Bit Symbol Read/Write Reset Value PB7 6 PB6 5 PB5 4 PB4 R/W 3 PB3 2 PB2 1 PB1 0 PB0 Input mode (The output latch is set to 1.) Port B Control Register 7 PBCR 0xFFFF_F057 Bit Symbol Read/Write Reset Value Function 0 PB7C 6 PB6C 0 5 PB5C 0 4 PB4C W 0 3 PB3C 0 2 PB2C 0 1 PB1C 0 0 PB0C 0 0: Input, 1: Output Port B Function Register 7 PBFC 0xFFFF_F05B Bit Symbol Read/Write Reset Value Function 0 0: PORT PB7F 6 PB6F 0 0: PORT 5 PB5F 0 0: PORT 1: TB3IN0 INT7 4 PB4F W 0 0: PORT 3 PB3F 0 0: PORT 2 PB2F 0 0: PORT 1: TB2IN0 INT5 1 PB1F 0 0: PORT 0 PB0F 0 0: PORT 1: TB3OUT 1: TB3IN1 INT8 1: TB2OUT 1: TB2IN1 INT6 1: TB1OUT 1: TB0OUT Function TB0OUT output settings TB1OUT output settings TB2IN0 input settings INT5 input settings TB2IN1 input settings INT6 input settings TB2OUT output settings TB3IN0 input settings INT7 input settings TB3IN1 input settings INT8 input settings TB3OUT output settings Corresponding Bit in PBFC 1 1 1 1 (*1) 1 1 (*1) 1 1 1(*1) 1 1(*1) 1 Corresponding Bit in PBCR 1 1 0 0 0 0 1 0 0 0 0 1 Port Used PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 *1: This bit must be set when the corresponding interrupt source is used for STOP wake-up signaling with SYSCR.DRVE cleared to 0. Otherwise, the bit need not be set. Note: For a port pin assigned two input functions in addition to the port function, the corresponding function modules must be programmed to determine which function is enabled. Figure 7.26 Port B Registers TMP1962-96 2006-02-21 TMP1962C10BXBG 7.11 Port C (PC0 - PC7) Eight Port C pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PCCR register selects the direction of the Port C pins. Upon reset, the PCCR register bits are cleared to all 0s, configuring all Port C pins as input port pins. PC0, PC3 and PC6 can be programmed as SIO data outputs. PC1, PC4 and PC7 can be programmed as SIO data inputs. PC2 and PC5 can be programmed as SIO clock inputs/outputs or CTS inputs. Setting the PCFC register bits configures the corresponding Port C pins for dedicated functions. A reset clears the PCCR and PCFC register bits, configuring all Port C pins as input port pins. Reset Direction Control (bitwise) PCCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PCFC Write S Output Latch A S Selector TXD0 Output TXD1 Output TXD2 Output PC Write B Configurable as open-drain outputs S Selector PC Read A B PCODE PC0 (TXD0) PC3 (TXD1) PC6 (TXD2) Figure 7.27 Port C (PC0, PC3, PC6) TMP1962-97 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PCCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PCFC Write S Output Latch PC1 (RXD0) PC4 (RXD1) PC7 (RXD2) S Selector PC Write B RXD0 Input RXD1 Input RXD2 Input PC Read A Figure 7.28 Port C (PC1, PC4, PC7) TMP1962-98 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PCCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PCFC Write S Output Latch A S Selector SCLK0 Output SCLK1 Output PC Write B Configurable as open-drain outputs PCODE PC2 (SCLK0/ CTS0 ) PC5 (SCLK1/ CTS1 ) S Selector PC Read CTS0 , CTS1 B A SCLK0, SCLK1 Figure 7.29 Port C (PC2, PC5) TMP1962-99 2006-02-21 TMP1962C10BXBG Port C Register 7 PC 0xFFFF_F052 Bit Symbol Read/Write Reset Value PC7 6 PC6 5 PC5 4 PC4 R/W 3 PC3 2 PC2 1 PC1 0 PC0 Input mode (The output latch is set to 1.) Port C Control Register 7 PCCR 0xFFFF_F056 Bit Symbol Read/Write Reset Value Function 0 PC7C 6 PC6C 0 5 PC5C 0 4 PC4C W 0 3 PC3C 0 2 PC2C 0 1 PC1C 0 0 PC0C 0 0: Input, 1: Output Port C Function Register 7 PCFC 0xFFFF_F05A Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: RXD2 PC7F 6 PC6F 0 0: PORT 1: TXD2 5 PC5F 0 0: PORT 1: SCLK1 CTS1 4 PC4F W 0 0: PORT 1: RXD1 3 PC3F 0 0: PORT 1: TXD1 2 PC2F 0 0: PORT 1: SCLK0 CTS0 1 PC1F 0 0: PORT 1: RXD0 0 PC0F 0 0: PORT 1: TXD0 Port C Open-Drain Enable Register 7 PCODE 0xFFFF_F05E Bit Symbol Read/Write Reset Value Function 1: - 6 PCODE6 W 0 0: CMOS 1: Open-dr ain 5 PCODE5 0 0: CMOS 4 - 3 PCODE3 W 0 0: CMOS 1: 1: Open-dr ain 2 PCODE2 0 0: CMOS 1 - 0 PCODE0 W 0 0: CMOS 1: Open-dr ain Open-dr ain Open-dr ain Figure 7.30 Port C Registers TMP1962-100 2006-02-21 TMP1962C10BXBG 7.12 Port D (PD0 - PD7) Eight Port D pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PDCR register selects the direction of the Port D pins. Upon reset, the PDCR register bits are cleared to all 0s, configuring all Port D pins as input port pins. PD0, PD3 and PD6 can be programmed as SIO clock inputs/outputs or CTS inputs. PD1 and PD4 can be programmed as SIO data outputs. PD2 and PD5 can be programmed as SIO data inputs. PD7 can be programmed as a key-pressed wake-up input. Setting the PDFC register bits configures the corresponding Port D pins for dedicated functions. A reset clears the PDCR and PDFC register bits, configuring all Port D pins as input port pins. PD7 has an internal pull-up resistor, which is enabled when key input is enabled through the programming of KWUPSTn with the KWUPCNT.KYPE bit set to 1 in the key-pressed wake-up circuit block. For details, refer to Chapter 19. The pull-up resistor is disabled when the PD7 pin is used as a general-purpose I/O pin. Reset Direction Control (bitwise) PDCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PDFC Write S Output Latch A S Selector SCLK2 Output SCLK3 Output SCLK4 Output PD Write B Configurable as open-drain outputs S Selector PD Read CTS2 , CTS3 PDODE PD0 (SCLK2/ CTS2 ) PD3 (SCLK3/ CTS3 ) PD6 (SCLK4/ CTS4 ) B A CTS4 SCLK2, SCLK3 SCLK4 Figure 7.31 Port D (PD0, PD3, PD6) TMP1962-101 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PDCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PDFC Write S Output Latch A S Selector PD Write TXD3 Output TXD4 Output B Configurable as open-drain outputs S Selector PD Read A B PDODE PD1 (TXD3) PD4 (TXD4) Figure 7.32 Port D (PD1, PD4) Reset Direction Control (bitwise) PDCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PDFC Write S Output Latch PD2 (RXD3) PD5 (RXD4) PD Write S Selector B PD Read RXD3 Input RXD4 Input A Figure 7.33 Port D (PD2, PD5) TMP1962-102 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) STOP DRIVE PDCR Write Internal Data Bus Function Control (bitwise) PDFC Write S Output Latch PD7 (KEY8) Reset PD Write S Selector PD Read A B KEY8 Figure 7.34 Port D (PD7) TMP1962-103 2006-02-21 TMP1962C10BXBG Port D Register 7 PD 0xFFFF_F051 Bit Symbol Read/Write Reset Value PD7 6 PD6 5 PD5 4 PD4 R/W 3 PD3 2 PD2 1 PD1 0 PD0 Input mode (The output latch is set to 1.) Port D Control Register 7 PDCR 0xFFFF_F055 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PD7C 6 PD6C 5 PD5C 4 PD4C W 3 PD3C 0 2 PD2C 0 1 PD1C 0 0 PD0C 0 0: Input, 1: Output Port D Function Register 7 PDFC 0xFFFF_F059 Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: KEY8 0 0: PORT 1: SCLK4 CTS4 6 PD6F 5 PD5F 0 0: PORT 1: RXD4 4 PD4F W 0 0: PORT 1: TXD4 3 PD3F 0 0: PORT 1: SCLK3 CTS3 2 PD2F 0 0: PORT 1: RXD3 1 PD1F 0 0: PORT 1: TXD3 0 PD0F 0 0: PORT 1: SCLK2 CTS2 PD7F Port D Open-Drain Enable Register 7 PDODE 0xFFFF_F05D Bit Symbol Read/Write Reset Value Function 1: Open-dr ain 6 PDODE6 W 0 0: CMOS 5 4 PDODE4 W 0 0: CMOS 1: Open-dr ain 1: 3 PDODE3 0 0: CMOS 2 1 PDODE1 W 0 0: CMOS 1: 1: Open-dr ain 0 PDODE0 0 0: CMOS Open-dr ain Open-dr ain Figure 7.35 Port D Registers TMP1962-104 2006-02-21 TMP1962C10BXBG 7.13 Port E (PE0 - PE7) Eight Port E pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PECR register selects the direction of the Port E pins. Upon reset, the PECR register bits are cleared to all 0s, configuring all Port E pins as input port pins. PE0 can be programmed as an SIO data output. PE1 can be programmed as an SIO data input. PE2 can be programmed as an SIO clock input/output or CTS input. PE3-PE7 can be programmed as key-pressed wake-up inputs. Setting the PEFC register bits configures the corresponding Port E pins for dedicated functions. A reset clears the PECR and PEFC register bits, configuring all Port E pins as input port pins. PE3-PE7 have internal pull-up resistors, which are enabled when key input is enabled through the programming of KWUPSTn with the KWUPCNT.KYPE bit set to 1 in the key-pressed wake-up circuit block. For details, refer to Chapter 19. The pull-up resistors are disabled when the PE3-PE7 pins are used as general-purpose I/O pins. Reset Direction Control (bitwise) PECR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PEFC Write S Output Latch A S Selector PE Write TXD5 Output S Selector PE Read A B B Configurable as an open-drain output PEODE PE0 (TXD5) Figure 7.36 Port E (PE0) TMP1962-105 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PECR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PEFC Write S Output Latch PE1 (RXD5) PE Write S Selector B PE Read RXD5 Input A Figure 7.37 Port E (PE1) Reset Direction Control (bitwise) PECR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PEFC Write S Output Latch A S Selector PE Write SCLK5 Output S Selector PE Read CTS5 PE2 (SCLK5/ CTS5 ) Configurable as an open-drain output PEODE B B A SCLK5 Figure 7.38 Port E (PE2) TMP1962-106 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) STOP DRIVE PECR Write Internal Data Bus Function Control (bitwise) PEFC Write S Output Latch PE3 (KEY9), PE4(KEYA) PE5 (KEYB), PE6(KEYC) PE7 (KEYD) Reset S Selector PE Write B PE Read KEY9, KEYA KEYB, KEYC KEYD A Figure 7.39 Port E (PE3, PE4, PE5, PE6, PE7) TMP1962-107 2006-02-21 TMP1962C10BXBG Port E Register 7 PE 0xFFFF_F050 Bit Symbol Read/Write Reset Value PE7 6 PE6 5 PE5 4 PE4 R/W 3 PE3 2 PE2 1 PE1 0 PE0 Input mode (The output latch is set to 1.) Port E Control Register 7 PECR 0xFFFF_F054 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PE7C 6 PE6C 5 PE5C 4 PE4C W 3 PE3C 0 2 PE2C 0 1 PE1C 0 0 PE0C 0 0: Input, 1: Output Port E Function Register 7 PEFC 0xFFFF_F058 Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: KEYD 0 0: PORT 1: KEYC 0 0: PORT 1: KEYB 0 0: PORT 1: KEYA PE7F 6 PE6F 5 PE5F 4 PE4F W 3 PE3F 0 0: PORT 1: KEY9 2 PE2F 0 0: PORT 1: SCLK5 CTS5 1 PE1F 0 0: PORT 1: RXD5 0 PE0F 0 0: PORT 1: TXD5 Port E Open-Drain Enable Register 7 PEODE 0xFFFF_F05C Bit Symbol Read/Write Reset Value Function 1: Open-dr ain 6 5 4 3 2 PEODE2 W 0 0: CMOS 1 0 PEODE0 W 0 0: CMOS 1: Open-dr ain Figure 7.40 Port E Registers TMP1962-108 2006-02-21 TMP1962C10BXBG 7.14 Port F (PF0 - PF7) Eight Port F pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PFCR register selects the direction of the Port F pins. Upon reset, the PFCR register bits are cleared to all 0s, configuring all Port F pins as input port pins. PF0-PF2 can be programmed as SBI inputs/outputs. PF3 and PF5 can be programmed as DMA request signal inputs. PF4 and PF6 can be programmed as DMA acknowledge signal outputs. PF7 can be programmed as a clock source input for the 32-bit time base timer. Setting the PFFC register bits configures the corresponding Port F pins for dedicated functions. A reset clears the PFCR and PFFC register bits, configuring all Port F pins as input port pins. Reset Direction Control (bitwise) PFCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PFFC Write S Output Latch A S Selector PF Write SO Output SDA Output B Configurable as an open-drain output PFODE PF0 (SO/SDA) Reset S Selector PF Read SDA Input B A Figure 7.41 Port F (PF0) TMP1962-109 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PFCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PFFC Write S Output Latch A S Selector PF Write SCL Output S Selector PF Read SI Input SCL Input A B B Configurable as an open-drain output PFODE PF1 (SI/SCL) Reset Figure 7.42 Port F (PF1) TMP1962-110 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PFCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PFFC Write S Output Latch A S Selector PF Write SCK Output S Selector PF Read SCK Input A B B PF2 (SCK) Reset Figure 7.43 Port F (PF2) TMP1962-111 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PFCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PFFC Write S Output Latch PF3 ( DREQ2 ) PF5 ( DREQ3 ) PF Write S Selector B DREQ2 Input DREQ3 Input PF Read A Figure 7.44 Port F (PF3, PF5) Reset Direction Control (bitwise) POCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus POFC Write S Output Latch A Selector DACK2 Output DACK3 Output S PF4 ( DACK2 ) PF6 ( DACK3 ) PO Write B S B Selector PO Read A Figure 7.45 Port F (PF4, PF6) TMP1962-112 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PFCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PFFC Write S Output Latch PF7 (TBTIN) PF Write S Selector B PF Read TBTIN A Figure 7.46 Port F (PF7) TMP1962-113 2006-02-21 TMP1962C10BXBG Port F Register 7 PF 0xFFFF_F063 Bit Symbol Read/Write Reset Value PF7 6 PF6 5 PF5 4 PF4 R/W 3 PF3 2 PF2 1 PF1 0 PF0 Input mode (The output latch is set to 1.) Port F Control Register 7 PFCR 0xFFFF_F067 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PF7C 6 PF6C 5 PF5C 4 PF4C W 3 PF3C 0 2 PF2C 0 1 PF1C 0 0 PF0C 0 0: Input, 1: Output Port F Function Register 7 PFFC 0xFFFF_F06B Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: TBTIN 0 0: PORT 1: DACK3 0 0: PORT 1: DREQ3 0 0: PORT 1: DACK 2 PF7F 6 PF6F 5 PF5F 4 PF4F W 3 PF3F 0 0: PORT 1: DREQ2 2 PF2F 0 0: PORT 1: SCK 1 PF1F 0 0: PORT 1: SI SCL 0 PF0F 0 0: PORT 1: SO SDAO Port F Open-Drain Enable Register 7 PFODE 0xFFFF_F06F Bit Symbol Read/Write Reset Value Function 1: Open-dr ain 0 0: CMOS 1: Open-dr ain 6 5 4 3 2 1 PFODE1 W 0 PFODE0 0 0: CMOS Figure 7.47 Port F Registers TMP1962-114 2006-02-21 TMP1962C10BXBG 7.15 Port G (PG0 - PG7) Eight Port G pins can be individually programmed to function as discrete general-purpose I/O pins or 32-bit capture trigger input pins. The PGCR register selects the direction of the Port G pins. Upon reset, the PGCR register bits are cleared to all 0s, configuring all Port G pins as input port pins. Setting the PGFC register bits configures the corresponding Port G pins as 32-bit capture trigger inputs. A reset clears the PGCR and PGFC register bits, configuring all Port G pins as input port pins. Reset Direction Control (bitwise) PGCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PGFC Write S Output Latch PG0 (TC0IN) PG1 (TC1IN) PG2 (TC2IN) PG3 (TC3IN) PG4 (TC4IN) PG5 (TC5IN) PG6 (TC6IN) PG7 (TC7IN) PG Write S Selector B TC0IN, TC1IN PG Read TC2IN, TC3IN TC4IN, TC5IN TC6IN, TC7IN A Figure 7.48 Port G (PG0 - PG7) TMP1962-115 2006-02-21 TMP1962C10BXBG Port G Register 7 PG 0xFFFF_F062 Bit Symbol Read/Write Reset Value PG7 6 PG6 5 PG5 4 PG4 R/W 3 PG3 2 PG2 1 PG1 0 PG0 Input mode (The output latch is set to 1.) Port G Control Register 7 PGCR 0xFFFF_F066 Bit Symbol Read/Write Reset Value Function 0 PG7C 6 PG6C 0 5 PG5C 0 4 PG4C W 0 3 PG3C 0 2 PG2C 0 1 PG1C 0 0 PG0C 0 0: Input, 1: Output Port G Function Register 7 PGFC 0xFFFF_F06A Bit Symbol Read/Write Reset Value Function PG7F W 0 0: PORT 1: TC7IN 6 PG6F 0 0: PORT 1: TC6IN 5 PG5F 0 0: PORT 1: TC5IN 4 PG4F 0 0: PORT 1: TC4IN 3 PG3F 0 0: PORT 1: TC3IN 2 PG2F 0 0: PORT 1: TC2IN 1 PG1F 0 0: PORT 1: TC1IN 0 PG0F 0 0: PORT 1: TC0IN Figure 7.49 Port G Registers TMP1962-116 2006-02-21 TMP1962C10BXBG 7.16 Port H (PH0 - PH7) Eight Port H pins can be individually programmed to function as discrete general-purpose I/O pins or 32-bit compare output pins. The PHCR register selects the direction of the Port H pins. Upon reset, the PHCR register bits are cleared to all 0s, configuring all Port H pins as input port pins. Setting the PHFC register bits configures the corresponding Port H pins as 32-bit compare outputs. A reset clears the PHCR and PHFC register bits, configuring all Port H pins as input port pins. Reset Direction Control (bitwise) PHCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PHFC Write S Output Latch A Selector Timer Flip-Flop PH Write Output TC0OUT, TC1OUT TC2OUT, TC3OUT TC4OUT, TC5OUT TC6OUT, TC7OUT PH Read B PH0 (TC0OUT) PH1 (TC1OUT) PH2 (TC2OUT) PH3 (TC3OUT) PH4 (TC4OUT) PH5 (TC5OUT) PH6 (TC6OUT) PH7 (TC7OUT) S S B Selector A Figure 7.50 Port H (PH0 - PH7) TMP1962-117 2006-02-21 TMP1962C10BXBG Port H Register 7 PH 0xFFFF_F061 Bit Symbol Read/Write Reset Value PH7 6 PH6 5 PH5 4 PH4 R/W 3 PH3 2 PH2 1 PH1 0 PH0 Input mode (The output latch is set to 1.) Port H Control Register 7 PHCR 0xFFFF_F065 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PH7C 6 PH6C 5 PH5C 4 PH4C W 3 PH3C 0 2 PH2C 0 1 PH1C 0 0 PH0C 0 0: Input, 1: Output Port H Function Register 7 PHFC 0xFFFF_F069 Bit Symbol Read/Write Reset Value Function 0 0: PORT 0 0: PORT 0 0: PORT 0 0: PORT PH7F 6 PH6F 5 PH5F 4 PH4F W 3 PH3F 0 0: PORT 2 PH2F 0 0: PORT 1 PH1F 0 0: PORT 0 PH0F 0 0: PORT 1: TCOUT7 1: TCOUT6 1: TCOUT5 1: TCOUT4 1: TCOUT3 1: TCOUT2 1: TCOUT1 1: TCOUT0 Figure 7.51 Port H Registers TMP1962-118 2006-02-21 TMP1962C10BXBG 7.17 Port I (PI0 - PI7) Eight Port I pins can be individually programmed to function as discrete general-purpose I/O pins or dedicated input pins. The PICR register selects the direction of the Port I pins. Upon reset, the PICR register bits are cleared to all 0s, configuring all Port I pins as input port pins. PI0 can be programmed as an trigger input for the A/D converter. PI1-PI6 can be programmed as external interrupt sources. Setting the PIFC register bits configures the corresponding Port I pins for dedicated functions. A reset clears the PICR and PIFC register bits, configuring all Port I pins as input port pins. Reset Direction Control (bitwise) PICR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PIFC Write S Output Latch PI0 ( ADTRG ) PI Write S Selector B PI Read ADTRG A Figure 7.52 Port I (PI0) TMP1962-119 2006-02-21 TMP1962C10BXBG Reset Function Control (bitwise) Direction Control (bitwise) STOP DRIVE PICR Write Internal Data Bus S Output Latch Output Buffer PI Write PI1 (INT1), PI2 (INT2) PI3 (INT3), PI4 (INT4) PI5 (INT9), PI6 (INTA) Reset INT1, INT2, INT3, INT4, INT9, INTA PI Read Figure 7.53 Port I (PI1 - PI6) Reset Direction Control (bitwise) STOP DRIVE PICR Write Internal Data Bus S Output Latch Output Buffer PI Write PI7 PI Read Figure 7.54 Port I (PI7) TMP1962-120 2006-02-21 TMP1962C10BXBG Port I Register 7 PI 0xFFFF_F060 Bit Symbol Read/Write Reset Value PI7 6 PI6 5 PI5 4 PI4 R/W 3 PI3 2 PI2 1 PI1 0 PI0 Input mode (The output latch is set to 1.) Port I Control Register 7 PICR 0xFFFF_F064 Bit Symbol Read/Write Reset Value Function 0 PI7C 6 PI6C 0 5 PI5C 0 4 PI4C W 0 3 PI3C 0 2 PI2C 0 1 PI1C 0 0 PI0C 0 0: Input, 1: Output Port I Function Register 7 PIFC 0xFFFF_F068 Bit Symbol Read/Write Reset Value Function 6 PI6F 0 0: PORT 1: INTA 5 PI5F 0 0: PORT 1: INT9 4 PI4F 0 0: PORT 1: INT4 3 PI3F W 0 0: PORT 1: INT3 2 PI2F 0 0: PORT 1: INT2 1 PI1F 0 0: PORT 1: INT1 0 PI0F 0 0: PORT 1: *ADTRG Function ADTRG output settings Corresponding Bit in PIFC 1 1 (*1) 1 (*1) 1 (*1) 1 (*1) 1 (*1) 1 (*1) Corresponding Bit in PICR 0 0 0 0 0 0 0 Port Used PI0 PI1 PI2 PI3 PI4 PI5 PI6 INT1 input settings INT2 input settings INT3 input settings INT4 input settings INT9 input settings INTA input settings *1: This bit must be set when the corresponding interrupt source is used for STOP wake-up signaling with SYSCR.DRVE cleared to 0. Otherwise, the bit need not be set. Figure 7.55 Port I Registers TMP1962-121 2006-02-21 TMP1962C10BXBG 7.18 Port J (PJ0 - PJ4) Five Port J pins can be individually programmed to function as discrete general-purpose I/O pins or dedicated input pins. The PJCR register selects the direction of the Port J pins. Upon reset, the PJCR register bits are cleared to all 0s, configuring all Port J pins as input port pins. PJ0 can be programmed as an external interrupt source. Setting the corresponding PJFC register bit configures PJ0 as an external interrupt source pin. A reset clears the PJCR and PJFC register bits, configuring all Port J pins as input port pins. Reset Function Control (bitwise) Direction Control (bitwise) STOP DRIVE PJCR Write Internal Data Bus S Output Latch Output Buffer Reset PJ Write PJ0 (INT0) PJ Read INT0 Figure 7.56 Port J (PJ0) TMP1962-122 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) STOP DRIVE PJCR Write Internal Data Bus S Output Latch Output Buffer PJ Write PJ1 - PJ4 PJ Read Figure 7.57 Port J (PJ1 - PJ4) TMP1962-123 2006-02-21 TMP1962C10BXBG Port J Register 7 PJ 0xFFFF_F0C3 Bit Symbol Read/Write Reset Value 6 5 4 PJ4 3 PJ3 2 PJ2 R/W 1 PJ1 0 PJ0 Input mode (The output latch is set to 1.) Port J Control Register 7 PJCR 0xFFFF_F0C7 Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 PJ4C 3 PJ3C 2 PJ2C W 0 0: Input, 1: Output 1 PJ1C 0 0 PJ0C 0 Port J Function Register 7 PJFC 0xFFFF_F0CB Bit Symbol Read/Write Reset Value Function 6 5 4 3 2 1 0 PJ0F W 0 0: PORT 1: INT0 Function INT0 input settings Corresponding Bit in PJFC 1 (*1) Corresponding Bit in PJCR 0 Port Used PJ0 *1: This bit must be set when the corresponding interrupt source is used for STOP wake-up signaling with SYSCR.DRVE cleared to 0. Otherwise, the bit need not be set. Figure 7.58 Port J Registers TMP1962-124 2006-02-21 TMP1962C10BXBG 7.19 Port K (PK0 - PK7) Eight Port K pins can be individually programmed to function as discrete general-purpose I/O pins or key-pressed wake-up input pins. The PKCR register selects the direction of the Port K pins. Upon reset, the PKCR register bits are cleared to all 0s, configuring all Port K pins as input port pins. Setting the PKFC register bits configures the corresponding Port K pins as key-pressed wake-up inputs. A reset clears the PKCR and PKFC register bits, configuring all Port K pins as input port pins. PK0-PK7 have internal pull-up resistors, which are enabled when key input is enabled through the programming of KWUPSTn with the KWUPCNT.KYPE bit set to 1 in the key-pressed wake-up circuit block. For details, refer to Chapter 19. The pull-up resistors are disabled when the PK0-PK7 pins are used as general-purpose I/O pins. Reset Direction Control (bitwise) STOP DRIVE PKCR Write Internal Data Bus Function Control (bitwise) PKFC Write S Output Latch PK0 (KEY0), PK1(KEY1) PK2 (KEY2), PK3(KEY3) PK4 (KEY4), PK5(KEY5) PK6 (KEY6), PK7(KEY7) Reset S Selector PK Read KEY0, KEY1 KEY2, KEY3 KEY4, KEY5 KEY6, KEY7 KEYmEN A B PK Write KYPE Figure 7.59 Port K (PK0 - PK7) TMP1962-125 2006-02-21 TMP1962C10BXBG Port K Register 7 PK 0xFFFF_F0C2 Bit Symbol Read/Write Reset Value PK7 6 PK6 5 PK5 4 PK4 R/W 3 PK3 2 PK2 1 PK1 0 PK0 Input mode (The output latch is set to 1.) Port K Control Register 7 PKCR 0xFFFF_F0C6 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PK7C 6 PK6C 5 PK5C 4 PK4C W 3 PK3C 0 2 PK2C 0 1 PK1C 0 0 PK0C 0 0: Input, 1: Output Port K Function Register 7 PKFC 0xFFFF_F0CA Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: KEY7 0 0: PORT 1: KEY6 0 0: PORT 1: KEY5 0 0: PORT 1: KEY4 PK7F 6 PK6F 5 PK5F 4 PK4F W 3 PK3F 0 0: PORT 1: KEY3 2 PK2F 0 0: PORT 1: KEY2 1 PK1F 0 0: PORT 1: KEY1 0 PK0F 0 0: PORT 1: KEY0 Figure 7.60 Port K Registers TMP1962-126 2006-02-21 TMP1962C10BXBG 7.20 Port L (PL0 - PL7) Eight Port L pins can be individually programmed to function as discrete general-purpose I/O pins or timer input pins. The PLCR register selects the direction of the Port L pins. Upon reset, the PLCR register bits are cleared to all 0s, configuring all Port L pins as input port pins. PL0-PL3 can be programmed as inputs to 8-bit timers. PL4-PL7 can be programmed as inputs to 16-bit timers. Setting the PLFC register bits configures the corresponding Port L pins for timer functions. A reset clears the PLCR and PLFC register bits, configuring all Port L pins as input port pins. Reset Direction Control (bitwise) PLCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PLFC Write S Output Latch PL0 (TA4IN) PL1 (TA6IN) PL2 (TA8IN) PL3 (TAAIN) PL4 (TB0IN0) PL5 (TB0IN1) PL6 (TB1IN0) PL7 (TB1IN1) PL Write S Selector B PL Read TA4IN, TA6IN TA8IN, TAAIN TB0IN0, TB0IN1 TB1IN0, TB1IN1 A Figure 7.61 Port L (PL0 - PL7) TMP1962-127 2006-02-21 TMP1962C10BXBG Port L Register 7 PL 0xFFFF_F0C1 Bit Symbol Read/Write Reset Value PL7 6 PL6 5 PL5 4 PL4 R/W 3 PL3 2 PL2 1 PL1 0 PL0 Input mode (The output latch is set to 1.) Port L Control Register 7 PLCR 0xFFFF_F0C5 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PL7C 6 PL6C 5 PL5C 4 PL4C W 3 PL3C 0 2 PL2C 0 1 PL1C 0 0 PL0C 0 0: Input, 1: Output Port L Function Register 7 PLFC 0xFFFF_F0C9 Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: TB1IN1 0 0: PORT 1: TB1IN0 0 0: PORT 1: TB0IN1 0 0: PORT 1: TB0IN0 PL7F 6 PL6F 5 PL5F 4 PL4F W 3 PL3F 0 0: PORT 1: TAAIN 2 PL2F 0 0: PORT 1: TA8IN 1 PL1F 0 0: PORT 1: TA6IN 0 PL0F 0 0: PORT 1: TA4IN Figure 7.62 Port L Registers TMP1962-128 2006-02-21 TMP1962C10BXBG 7.21 Port M (PM0 - PM7) Eight Port M pins can be individually programmed to function as discrete general-purpose I/O pins. The PMCR register selects the direction of the Port M pins. Upon reset, the PMCR register bits are cleared to all 0s, configuring all Port M pins as input port pins. Reset Direction Control (bitwise) STOP DRIVE PMCR Write Internal Data Bus S Output Latch Output Buffer PM Write PM0 - PM7 PM Read Figure 7.63 Port M (PM0 - PM7) TMP1962-129 2006-02-21 TMP1962C10BXBG Port M Register 7 PM 0xFFFF_F0C0 Bit Symbol Read/Write Reset Value PM7 6 PM6 5 PM5 4 PM4 R/W 3 PM3 2 PM2 1 PM1 0 PM0 Input mode (The output latch is set to 1.) Port M Control Register 7 PMCR 0xFFFF_F0C4 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PM7C 6 PM6C 5 PM5C 4 PM4C W 3 PM3C 0 2 PM2C 0 1 PM1C 0 0 PM0C 0 0: Input, 1: Output Figure 7.64 Port M Registers TMP1962-130 2006-02-21 TMP1962C10BXBG 7.22 Port N (PN0 - PN7) Eight Port N pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. The PNCR register selects the direction of the Port N pins. Upon reset, the PNCR register bits are cleared to all 0s, configuring all Port N pins as input port pins. PN0 can be programmed as an SIO data output. PN1 can be programmed as an SIO data input. PN2 can be programmed as an SIO clock input/output or CTS input. Setting the PNFC register bits configures the corresponding Port N pins for dedicated functions. A reset clears the PNCR and PNFC register bits, configuring all Port N pins as input port pins. Reset Direction Control (bitwise) PNCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PNFC Write S Output Latch A S Selector PN Write TXD6 Output S Selector PN Read A B B Configurable as an open-drain output PNODE PN0 (TXD6) Figure 7.65 Port N (PN0) TMP1962-131 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) PNCR Write STOP DRIVE Internal Data Bus Function Control (bitwise) PNFC Write S Output Latch PN1 (RXD6) PN Write S Selector B PN Read RXD6 Input A Figure 7.66 Port N (PN1) Reset Direction Control (bitwise) PNCR Write STOP DRIVE Function Control (bitwise) Internal Data Bus PNFC Write S Output Latch A S Selector PN Write SCLK6 Output S Selector PN Read CTS6 Input PN2 (SCLK6/ CTS6 ) Configurable as an open-drain output PNODE B B A SCLK6 Input Figure 7.67 Port N (PN2) TMP1962-132 2006-02-21 TMP1962C10BXBG Reset Direction Control (bitwise) STOP DRIVE PNCR Write Internal Data Bus S Output Latch Output Buffer PN Write PN3 - PN7 PN Read Figure 7.68 Port N (PN3 - PN7) TMP1962-133 2006-02-21 TMP1962C10BXBG Port N Register 7 PN 0xFFFF_F0D3 Bit Symbol Read/Write Reset Value PN7 6 PN6 5 PN5 4 PN4 R/W 3 PN3 2 PN2 1 PN1 0 PN0 Input mode (The output latch is set to 1.) Port N Control Register 7 PNCR 0xFFFF_F0D7 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PN7C 6 PN6C 5 PN5C 4 PN4C W 3 PN3C 0 2 PN2C 0 1 PN1C 0 0 PN0C 0 0: Input, 1: Output Port N Function Register 7 PNFC 0xFFFF_F0DB Bit Symbol Read/Write Reset Value Function 0 0: PORT 1: SCLK6 *CTS6 6 5 4 3 2 PN2F 1 PN1F W 0 0: PORT 1: RXD6 0 PN0F 0 0: PORT 1: TXD6 Port N Open-Drain Enable Register 7 PNODE 0xFFFF_F0DF Bit Symbol Read/Write Reset Value Function 1: Open-dr ain 6 5 4 3 2 PNODE2 W 0 0: CMOS 1 0 PNODE0 W 0 0: CMOS 1: Open-dr ain Figure 7.69 Port N Registers TMP1962-134 2006-02-21 TMP1962C10BXBG 7.23 Port O and Port P (PO0 - PO7, PP0 - PP7) Eight Port O pins and eight Port P pins can be individually programmed to function as discrete general-purpose I/O pins. The POCR and PPCR registers select the direction of the Port O and P pins, respectively. Upon reset, the POCR and PPCR register bits are cleared to all 0s, configuring all Port O and P pins as input port pins. Reset Direction Control (bitwise) STOP DRIVE POCR/PPCR Write Internal Data Bus S Output Latch Output Buffer PO/PP Write PO0 - PO7 PP0 - PP7 PO/PP Read Figure 7.70 Port O and Port P (PO0 - PO7, PP0 - PP7) TMP1962-135 2006-02-21 TMP1962C10BXBG Port O Register 7 PO 0xFFFF_F0D2 Bit Symbol Read/Write Reset Value PO7 6 PO6 5 PO5 4 PO4 R/W 3 PO3 2 PO2 1 PO1 0 PO0 Input mode (The output latch is set to 1.) Port O Control Register 7 POCR 0xFFFF_F0D6 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PO7C 6 PO6C 5 PO5C 4 PO4C W 3 PO3C 0 2 PO2C 0 1 PO1C 0 0 PO0C 0 0: Input, 1: Output Figure 7.71 Port O Registers Port P Register 7 PP 0xFFFF_F0D1 Bit Symbol Read/Write Reset Value PP7 6 PP6 5 PP5 4 PP4 R/W 3 PP3 2 PP2 1 PP1 0 PP0 Input mode (The output latch is set to 1.) Port P Control Register 7 PPCR 0xFFFF_F0D5 Bit Symbol Read/Write Reset Value Function 0 0 0 0 PP7C 6 PP6C 5 PP5C 4 PP4C W 3 PP3C 0 2 PP2C 0 1 PP1C 0 0 PP0C 0 0: Input, 1: Output Figure 7.72 Port P Registers TMP1962-136 2006-02-21 TMP1962C10BXBG 8. External Bus Interface The TMP1962 contains external bus interface logic that handles the transfer of information between the internal buses and the memory or peripherals in the external address space. It consists of the External Bus Interface (EBIF) logic and the Chip Select/Wait Controller. The CS/Wait Controller provides four programmable chip select signals, with variable block sizes. The chip select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four address blocks and the rest of the external address locations. The EBIF logic controls the timing of the external bus, based on the settings of the CS/Wait Controller. The EBIF logic also performs dynamic bus sizing and bus arbitration. * External bus mode Address/Data Separate Bus mode or Multiplexed Bus mode * * * * Wait-state generation Individually programmable for each address block Automatic insertion of up to seven wait cycles Insertion of wait cycles through the WAIT / RDY pin Data bus width Individually programmable (8-bit or 16-bit) for each address block * Recovery cycles (read and write) Individually programmable (to up to 2 cycles) for each address block. Recovery cycles are dummy cycles inserted between two consecutive external bus cycles. * Bus arbitration TMP1962-137 2006-02-21 TMP1962C10BXBG 8.1 Address and Data Buses (1) Supported configurations The TMP1962 supports the selection of either Separate Bus mode or Multiplexed Bus mode. If the BUSMD pin (Port J1) is driven low upon reset, Separate Bus mode is selected. If the BUSMD pin is driven high upon reset, Multiplexed Bus mode is selected. For external memory interface, Port 0, Port 1, Port 2, Port 5 and Port 6 pins can be configured as the address bus, data bus or address/data bus. Table 8.1 shows the usage of the port pins in Separate and Multiplexed Bus modes. Table 8.1 Usage of Port Pins in Separate and Multiplexed Bus Modes Separate Bus Mode (BUSMD = L) Port 0 (P00 - P07) Port 1 (P10 - P17) Port 2 (P20 - P27) Port 5 (P50 - P57) Port 6 (P60 - P67) Port 3 (P37 only) D0 - D7 D8 - D15 A16 - A23 A0 - A7 A8 - A15 General-purpose port Multiplexed Bus Mode (BUSMD = H) AD0 - AD7 AD8 - AD15/A8 - A15 A0 - A7/A16 - A23 General-purpose port General-purpose port ALE Upon reset, all port pins are configured as general-purpose input port pins. For external memory accesses, port pins must be configured as the address or data bus through the programming of the corresponding Port Control Register (PnCR) and Port Function Register (PnFC). In Multiplexed Bus mode, the TMP1962 supports the following four bus configurations, according to the settings in the PnCR and PnFC. Table 8.2 Address and Data Pins in Multiplexed Bus Mode (1) Address Lines Data Lines Multiplexed Address/Data Lines Pin Functions Port 0 Port 1 Port 2 max.24 ( - 16 MB) 8 8 AD0 - AD7 A8 - A15 A16 - A23 (2) max.24 ( - 16 MB) 16 16 AD0 - AD7 AD8 - AD15 A16 - A23 (3) max.16 ( - 64 KB) 8 0 AD0 - AD7 A8 - A15 A0 - A7 (4) max.8 ( - 256 B) 16 0 AD0 - AD7 AD8 - AD15 A0 - A7 A23 - 8 A23 - 8 A23 - 16 A23 - 16 A15 - 0 A15 - 0 (Note 1) A7 - 0 A7 - 0 (Note 1) AD7 - 0 A7 - 0 D7 - 0 AD15 - 0 Timing Diagram ALE ALE A15 -0 D15 -0 AD7 - 0 A7 - 0 D7 - 0 A15 AD15 - 0 -0 ALE D15 -0 ALE RD RD RD RD Note 1: Because the data bus is multiplexed with the address bus, even in the (3) and (4) configurations, address bits also appear on the AD bus prior to the data being accepted or provided. Note 2: Upon reset, all of Ports 0-2 are configured as general-purpose input ports; programming is required to use them as address or data bus pins. Note 3: Address and data bus configurations are selectable through the programming of the P1CR, P1FC, P2CR and P2FC registers. TMP1962-138 2006-02-21 TMP1962C10BXBG (2) States of the address bus during on-chip address accesses While an on-chip address is being accessed, the address bus maintains the previous address externally presented. During this time, the data bus assumes the high-impedance state. 8.2 Data Formats This section shows the relationship between the external bus interface and the TMP1962 internal register assignments. (1) Big-Endian mode 1) Word access * 16-bit bus Internal Register address D31 AA BB CC D00 DD x0 x1 x2 x3 MSB A1 = 0 AABB LSB A1 = 1 CCDD External Bus * 8-bit bus Internal Register address D31 AA BB CC D00 DD x0 x1 x2 x3 AA x0 BB x1 CC x2 DD x3 External Bus 2) Halfword access * 16-bit bus Internal Register address D31 MSB AA D00 BB x0 x1 address D31 CC D00 DD x2 x3 MSB CCDD LSB AABB LSB External Bus TMP1962-139 2006-02-21 TMP1962C10BXBG * 8-bit bus Internal Register address D31 AA D00 BB x0 x1 AA x0 BB x1 External Bus Internal Register address D31 CC D00 DD x2 x3 External Bus CC x2 DD x3 3) Byte access * 16-bit bus Internal Register address D31 AA MSB D00 AA x0 address D31 MSB D00 BB x1 address D31 CC MSB D00 CC x2 address D31 MSB D00 DD x3 DD LSB LSB BB LSB LSB External Bus TMP1962-140 2006-02-21 TMP1962C10BXBG * 8-bit bus Internal Register address D31 AA External Bus D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 (2) Little-Endian mode 1) Word access * 16-bit bus Internal Register address D31 DD CC BB D00 AA x3 x2 x1 x0 LSB AABB MSB A1 = 0 A1 = 1 CCDD External Bus * 8-bit bus Internal Register address D31 DD CC BB D00 AA x3 x2 x1 x0 AA x0 BB x1 CC x2 DD x3 External Bus TMP1962-141 2006-02-21 TMP1962C10BXBG 2) Halfword access * 16-bit bus Internal Register address D31 LSB BB D00 AA x1 x0 address D31 DD D00 CC x3 x2 LSB CCDD MSB AABB MSB External Bus * 8-bit bus Internal Register address D31 BB D00 AA x1 x0 AA x0 BB x1 External Bus Internal Register address D31 DD D00 CC x3 x2 External Bus CC x2 DD x3 TMP1962-142 2006-02-21 TMP1962C10BXBG 3) Byte access * 16-bit bus Internal Register address D31 AA LSB D00 AA x0 address D31 LSB D00 BB x1 address D31 CC LSB D00 CC x2 address D31 LSB D00 DD x3 DD MSB MSB BB MSB MSB External Bus * 8-bit bus Internal Register address D31 AA External Bus D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 TMP1962-143 2006-02-21 TMP1962C10BXBG 8.3 External Bus Operation (Separate Bus Mode) This section describes external bus operations. In the timing diagrams which follow, A23-A0 are used as the address bus, and D15-D0 are used as the data bus. (1) Basic bus operation While the TMP1962 provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. The internal system clock is also used as the basic clock for external bys cycles. Figure 8.1 shows external bus read timing. Figure 8.2 shows external bus write timing. While an on-chip address is being accessed, the external address bus maintains the previous value. During this time, the data bus assumes the high-impedance state, and bus control signals such as RD and WR remain inactive. tsys CSn A [23:0] D [15:0] DATA No change Hi-Z RD External access Inactive Internal access Figure 8.1 Read Cycle Timing tsys CSn A [23:0] D [15:0] No change Hi-Z DATA WR Inactive External access Internal access Figure 8.2 Write Cycle Timing TMP1962-144 2006-02-21 TMP1962C10BXBG (2) Wait timing The CS/Wait Controller provides three ways to insert wait states in a bus cycle for each address block: 1) Inserting required number of wait state cycles automatically (up to seven cycles) 2) Using the WAIT pin to insert wait states dynamically (1+N, 3+N, 5+N or 7+N, where N is the number of wait state cycles inserted) 3) Using the RDY pin to insert wait states dynamically (1+N, 3+N, 5+N or 7+N, where N is the number of wait state cycles inserted) The BnW bit of the CS/Wait Control Register (BmnCS) defines the number of wait state cycles to be inserted automatically as well as external wait state input settings. Figure 8.3 through 8.12 show bus cycle timings with wait states. tsys A [23:0] address address D [15:0] data data RD 0 Wait State 1 Wait State Figure 8.3 Read Cycle Timing (with Zero and Automatically Inserted One Wait State) tsys A [23:0] address D [15:0] data RD 5 Wait States Figure 8.4 Read Cycle Timing (with Automatically Inserted Five Wait States) TMP1962-145 2006-02-21 TMP1962C10BXBG tsys A [23:0] address address D [15:0] data data RD WAIT 0 Wait State External (1 + N) Wait States; N = 1 Figure 8.5 Read Cycle Timing (with Externally Inserted (1 + N) Wait States; N = 1) tsys A [23:0] address D [15:0] data RD WAIT External (3 + N) Wait States; N = 1 Figure 8.6 Read Cycle Timing (with Externally Inserted (3 + N) Wait States; N = 1) tsys A [23:0] address D [15:0] data RD WAIT External (3 + N) Wait States; N = 3 Figure 8.7 Read Cycle Timing (with Externally Inserted (3 + N) Wait States; N = 3) TMP1962-146 2006-02-21 TMP1962C10BXBG tsys A [23:0] address address D [15:0] data data WR 0 Wait State 1 Wait State Figure 8.8 Write Cycle Timing (with Zero and Automatically Inserted One Wait State) tsys A [23:0] address D [15:0] data WR 5 Wait States Figure 8.9 Write Cycle Timing (with Automatically Inserted Five Wait States) TMP1962-147 2006-02-21 TMP1962C10BXBG tsys A [23:0] address address D [15:0] data data WR WAIT 0 Wait State External (1 + N) Wait States; N = 1 Figure 8.10 Write Cycle Timing (with Externally Inserted (1 + N) Wait States; N = 1) tsys A [23:0] address D [15:0] data WR WAIT External (3 + N) Wait States; N = 1 Figure 8.11 Write Cycle Timing (with Externally Inserted (3 + N) Wait States; N = 1) tsys A [23:0] address D [15:0] data WR WAIT External (3 + N) Wait States; N = 3 Figure 8.12 Write Cycle Timing (with Externally Inserted (3 + N) Wait States; N = 3) TMP1962-148 2006-02-21 TMP1962C10BXBG Setting bit 3 (P33F) of the Port 3 Function Register (P3FC) to 1 configures the WAIT input pin (P33) as the RDY input pin. The input supplied from the RDY pin to the external bus interface block is the logical negation of the WAIT input. The BnW bit of the CS/Wait Control Register (BmnCS) defines the number of wait state cycles to be inserted. Figure 8.13 through 8.15 show wait states inserted with the RDY input. tsys A [23:0] address address D [15:0] data data RD RDY 0 Wait State External (1 + N) Wait States; N = 1 Figure 8.13 RDY Input Timing (with Externally Inserted (1 + N) Wait States; N = 1) tsys A [23:0] address D [15:0] data RD RDY External (3 + N) Wait States; N = 1 Figure 8.14 RDY Input Timing (with Externally Inserted (3 + N) Wait States; N = 1) TMP1962-149 2006-02-21 TMP1962C10BXBG tsys A [23:0] address D [15:0] data RD RDY External (3 + N) Wait States; N = 3 Figure 8.15 RDY Input Timing (with Externally Inserted (3 + N) Wait States; N = 3) (3) ALE pulse width When the TMP1962 external buses are used in Multiplexed Bus mode, the ALE pulse width can be programmed through the ALESEL bit of the SYSCR3 register within the CG. In Separate Bus mode, ALE is not asserted but the value of the SYSCR3.ALESEL bit determines the time between an address being established and RD or WR being asserted. Upon reset, ALESEL is set to 1, so that RD or WR is asserted two (internal) system clock cycles after an address is established. Clearing ALESEL to 0 causes RD or WR to be asserted one system clock cycle after an address is established. This setting applies to the whole external address space. tsys A [23:0] address address D [15:0] data data RD Figure 8.16 SYSCR3.ALESEL Setting and External Bus Operation TMP1962-150 2006-02-21 TMP1962C10BXBG (4) Recovery time Following an external bus cycle, a certain recovery time may be required before initiating the next external bus cycle. To allow for a recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. Dummy cycles can be inserted either after a read cycle or a write cycle. Dummy cycle insertion is programmable with the BnWCV (write recovery cycle) and BnRCV (read recovery cycle) bits of the CS/Wait Control Register (BmnCS). The number of dummy cycles (one or two internal system clock cycles) can be specified for each block. Figure 8.17 shows timing with a recovery time inserted. tsys CS A [23:0] address next address RD WR No Recovery Cycle tsys CS A [23:0] address next address RD WR 1 Recovery Cycle 2 Recovery Cycles Figure 8.17 Timing with a Recovery Time Inserted TMP1962-151 2006-02-21 TMP1962C10BXBG 8.4 External Bus Operation (Multiplexed Bus Mode) This section describes external bus operations. In the timing diagrams which follow, A23-A16 are used as the address bus, and AD15-AD0 are used as the address/data bus. (1) Basic bus operation While the TMP1962 provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. The internal system clock is also used as the basic clock for external bys cycles. Figure 8.18 shows external bus read timing. Figure 8.19 shows external bus write timing. While an on-chip address is being accessed, the external address bus maintains the previous value with the ALE pin kept inactive. During this time, the address/data bus assumes the high-impedance state, and bus control signals such as RD and WR remain inactive. tsys CSn A [23:16] No change ADR Hi-Z DATA Inactive Inactive AD [15:0] ALE RD External access Internal access Figure 8.18 Read Cycle Timing tsys CSn A [23:16] No change ADR DATA Hi-Z AD [15:0] ALE WR Inactive Inactive External access Internal access Figure 8.19 Write Cycle Timing TMP1962-152 2006-02-21 TMP1962C10BXBG (2) Wait timing The CS/Wait Controller provides three ways to insert wait states in a bus cycle for each address block: 1) Inserting required number of wait state cycles automatically (up to seven cycles) 2) Using the WAIT pin to insert wait states dynamically (1+N, 3+N, 5+N or 7+N, where N is the number of wait state cycles inserted) 3) Using the RDY pin to insert wait states dynamically (1+N, 3+N, 5+N or 7+N, where N is the number of wait state cycles inserted) The BnW bit of the CS/Wait Control Register (BmnCS) defines the number of wait state cycles to be inserted automatically as well as external wait state input settings. Figure 8.20 through 8.29 show bus cycle timings with wait states. Wait State tsys A [23:16] Upper Address Upper Address AD [15:0] ALE ADR DATA ADR DATA RD 0 Wait State 1 Wait State Figure 8.20 Read Cycle Timing (with Zero and One Wait State) Wait State tsys A [23:16] Upper Address AD [15:0] ALE ADR DATA RD 5 Wait States Figure 8.21 Read Cycle Timing (with Five Wait States) TMP1962-153 2006-02-21 TMP1962C10BXBG Wait State tsys A [23:16] Upper Address Upper Address AD [15:0] ALE RD ADR DATA ADR DATA WAIT 0 Wait State (1 + N) Wait States; N = 1 Wait Figure 8.22 Read Cycle Timing (with (1 + N) Wait States; N = 1) Wait State tsys A [23:16] Upper Address AD [15:0] ALE RD ADR DATA WAIT (3 + N) Wait States; N = 1 Figure 8.23 Read Cycle Timing (with (3 + N) Wait States; N = 1) Wait State tsys A [23:16] Upper Address AD [15:0] ALE RD ADR DATA WAIT (3 + N) Wait States; N = 3 Figure 8.24 Read Cycle Timing (with (3 + N) Wait States; N = 3) TMP1962-154 2006-02-21 TMP1962C10BXBG Wait State tsys A [23:16] Upper Address Upper Address AD [15:0] ADR DATA ADR DATA ALE WR 0 Wait State 1 Wait State Figure 8.25 Write Cycle Timing (with Zero and One Wait State) Wait State tsys A [23:16] Upper Address AD [15:0] ADR DATA ALE WR 5 Wait States Figure 8.26 Write Cycle Timing (with Five Wait States) TMP1962-155 2006-02-21 TMP1962C10BXBG Wait State tsys Upper Address Upper Address A [23:16] AD [15:0] ADR DATA ADR DATA ALE WR WAIT 0 Wait State (1 + N) Wait States; N = 1 Figure 8.27 Write Cycle Timing (with (1 + N) Wait States; N = 1) Wait State tsys A [23:16] Upper Address AD [15:0] ADR DATA ALE WR WAIT (3 + N) Wait States; N = 1 Figure 8.28 Write Cycle Timing (with (3 + N) Wait States; N = 1) Wait State tsys A [23:16] Upper Address AD [15:0] ALE ADR DATA WR WAIT (3 + N) Wait States; N = 3 Figure 8.29 Write Cycle Timing (with (3 + N) Wait States; N = 3) TMP1962-156 2006-02-21 TMP1962C10BXBG (3) ALE pulse width The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external address space. tsys ALE (ALESEL = 0) 0.5 Clock Cycles AD [15:0] (ALESEL = 1) 1.5 Clock Cycles AD [15:0] Figure 8.30 ALE Pulse Width Figure 8.31 shows read cycle timing, with the ALE width programmed to 0.5 and 1.5 clock cycles. tsys A [23:16] Upper Address Upper Address AD [15:0] ADR DATA ADR DATA ALE RD ALE = 0.5 Clock Cycles ALE = 1.5 Clock Cycles Figure 8.31 Read Cycle Timing (ALE = 0.5 and 1.5 Clock Cycles) Note: In the TMP1962F10, configuring the ALE pulse width as 0.5 or 1.5 clock cycles results in the actual ALE pulse width being 1.5 or 2.5 clock cycles, respectively. TMP1962-157 2006-02-21 TMP1962C10BXBG (4) Recovery time Following an external bus cycle, a certain recovery time may be required before initiating the next external bus cycle. To allow for a recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. Dummy cycles can be inserted either after a read cycle or a write cycle. Dummy cycle insertion is programmable with the BnWCV (write recovery cycle) and BnRCV (read recovery cycle) bits of the CS/Wait Control Register (BmnCS). The number of dummy cycles (one or two internal system clock cycles) can be specified for each block. Figure 8.32 shows timing with a recovery time inserted. tsys CS A [23:0] address next address RD WR No Recovery Cycle tsys CS A [23:0] address next address RD WR 1 Recovery Cycle 2 Recovery Cycles Figure 8.32 Timing with a Recovery Time Inserted TMP1962-158 2006-02-21 TMP1962C10BXBG 8.5 Bus Arbitration The TMP1962 provides support for an external bus master to take control of the external bus. Two bus arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the TMP1962 internal bus. (1) Bus access control External bus masters can gain control of the external bus, but not the TMP1962 internal bus (G-Bus). Thus, external bus masters cannot access the TMP1962's on-chip memory and peripherals. The External Bus Interface (EBIF) logic in the TMP1962 manages the arbitration of the external bus; the CPU and on-chip DMAC do not participate in any way in this bus arbitration. During external bus mastership, the CPU and the on-chip DMAC can access the internal memory (RAM and ROM) and registers. Once an external device assumes bus mastership, the CPU or the on-chip DMAC has no way to regain the bus until the external bus master releases the bus. If the CPU or the on-chip DMAC issues an external memory access request, it is forced to wait until the TMP1962 regains the bus. Therefore, should BUSRQ be left asserted for a long time, the TMP1962 might suffer system lockups. (2) Bus arbitration flow External devices capable of becoming bus masters assert BUSRQ to request the bus. The TMP1962 samples BUSRQ at the end of each external bus cycle, as seen on its internal bus (GBus). When the TMP1962 has made an internal decision to grant the bus, it asserts BUSAK to indicate to the requesting device that the bus is available. At the same time, the TMP1962 puts the address bus, the data bus and bus control signals in the high-impedance state. A load or store may require multiple bus cycles, depending on the port size of the addressed device (dynamic bus sizing). In that case, the TMP1962 does not grant the bus until the entire transfer is complete. The TMP1962, if so programmed, automatically inserts dummy cycles between back-to-back bus cycles to allow for sufficient read recovery time. In dummy cycles, the TMP1962 has already internally initiated a bus cycle on the G-Bus for the next external access. The TMP1962 can only accept an external bus request at the boundary of an internal G-Bus bus cycle. Therefore, if BUSRQ is asserted during a dummy cycle, the TMP1962 grants the bus after it completes the next external bus cycle. An external bus master must keep BUSRQ asserted until it is granted the bus. A timing diagram of the bus arbitration sequence is shown in Figure 8.33. TMP1962-159 2006-02-21 TMP1962C10BXBG (1) (2) (3) tsys Internal Address External Address BUSRQ TMP1962 external access TMP1962 external access External bus master cycle TMP1962 external access TMP1962 external access BUSAK 1) BUSRQ is sampled high. 2) The TMP1962 recognizes the assertion of BUSRQ . 3) The TMP1962 asserts BUSAK at the completion of the current bus cycle. The external bus master recognizes BUSAK and assumes bus mastership to start a bus transfer. Figure 8.33 Bus Arbitration Timing Diagram (3) Relinquishing the bus The external bus master relinquishes the bus when it has completed its bus transactions and no longer requires the bus. When the external bus master has completed its bus transactions, it de-asserts BUSRQ to relinquish the bus to the TMP1962. Figure 8.34 shows the timing for an external bus master to relinquish the bus. (1) (2)(3) tsys Internal Address External Address BUSRQ TMP1962 external access TMP1962 external External bus master cycle TMP1962 external access TMP1962 external access BUSAK 1) The external bus master has control of the bus. 2) When the external bus master no longer needs the bus, it de-asserts BUSRQ . 3) In response to the de-assertion of BUSRQ , the TMP1962 de-asserts BUSAK . Figure 8.34 External Bus Master Relinquishing the Bus TMP1962-160 2006-02-21 TMP1962C10BXBG 9. Chip Select/Wait Controller The TMP1962 supports direct connections to external devices (I/O devices, ROM and SRAM). The TMP1962 provides four programmable chip select signals. Programmable features include variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles. CS0 - CS3 (multiplexed with P40-P43) are the chip select output pins for the CS0-CS3 address ranges. These chip select signals are generated when the CPU or on-chip DMAC issues an address within the programmed ranges. The P40-P43 pins must be configured as CS0-CS3 by programming the Port 4 Control (P4CR) register and the Port 4 Function (P4FC) register. Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3. There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. External memory devices can also use the WAIT pin to insert wait states and consequently prolong read and write bus cycles. 9.1 Programming Chip Select Ranges Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model allows one of the chip select output signals ( CS0 - CS3 ) to assert when an address on the address bus falls within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1, and the B23CS register defines specific operations for CS2 and CS3 (see Section 9.2). 9.1.1 Base/Mask Address Registers The organizations of the BMAn registers are shown in Figure 9.1 and Figure 9.2. The base address (BAn) field specifies the starting address for a chip select. Any set bit in the address mask field (MAn) masks the corresponding base address bit. The address mask field determines the block size of a particular chip select line. The address is compared on every bus cycle. (1) Base address The base address (BAn) field specifies the upper 16 bits (A31-A16) of the starting address for a chip select. The lower 16 bits (A15-A0) are assumed to be zero. Thus, the base address is any multiple of 64 Kbytes starting at 0x0000_0000. Figure 9.3 shows the relationships between starting addresses and the BMAn values. (2) Address mask The address mask (MAn) field defines whether any particular bits of the address should be compared or masked. Any set bit masks the corresponding base address bit. The address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match. Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as follows: CS0 and CS1 spaces: A29-A14 CS2 and CS3 spaces: A30-A15 Note: Use physical addresses in the BMAn registers. TMP1962-161 2006-02-21 TMP1962C10BXBG Base/Mask Address Registers: BMA0 (0xFFFF_E400) to BMA3 (0xFFFF_E40C) 31 BMA0 (0xFFFF_E400) Bit Symbol Read/Write Reset Value Function 0 0 0 0 30 29 28 BA0 R/W 27 26 25 24 0 0 0 0 A31-A24 of the starting address 23 Bit Symbol Read/Write Reset Value Function 0 22 21 20 BA0 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address 15 Bit Symbol Read/Write Reset Value Function 0 14 13 12 MA0 R/W 11 10 9 8 0 0 0 0 0 1 1 Must be written as 0. 7 Bit Symbol Read/Write Reset Value Function 1 6 5 4 MA0 R/W 3 2 1 0 1 1 1 1 1 1 1 CS0 block size 0: The address compare logic uses this address bit. 31 BMA1 (0xFFFF_E404) Bit Symbol Read/Write Reset Value Function 0 30 29 28 BA1 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address 23 Bit Symbol Read/Write Reset Value Function 0 22 21 20 BA1 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address 15 Bit Symbol Read/Write Reset Value Function 0 14 13 12 MA1 R/W 11 10 9 8 0 0 0 0 0 1 1 Must be written as 0. 7 Bit Symbol Read/Write Reset Value Function Note: 1 6 5 4 MA1 R/W 3 2 1 0 1 1 1 1 1 1 1 CS1 block size 0: The address compare logic uses this address bit. Bits 10-15 in the BMA0 and BMA1 must be written as zeros. The CS0 and CS1 block sizes can vary from 16 Kbytes to 1 Gbyte. However, the TMP1962 supports only 16 Mbytes of external address space. Therefore, bits 10-15 in the BMA0 and BMA1 must be cleared so that A24-A29 of an address will not be masked. Figure 9.1 Base/Mask Address Registers (BMA0 and BMA1) TMP1962-162 2006-02-21 TMP1962C10BXBG 31 BMA2 (0xFFFF_E408) Bit Symbol Read/Write Reset Value Function 0 30 29 28 BA2 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address 23 Bit Symbol Read/Write Reset Value Function 0 22 21 20 BA2 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address 15 Bit Symbol Read/Write Reset Value Function 0 14 13 12 MA2 R/W 11 10 9 8 0 0 0 Must be written as 0. 0 0 0 1 7 Bit Symbol Read/Write Reset Value Function 1 6 5 4 MA2 R/W 3 2 1 0 1 1 1 1 1 1 1 CS2 block size 0: The address compare logic uses this address bit. 31 BMA3 (0xFFFF_E40C) Bit Symbol Read/Write Reset Value Function 0 30 29 28 BA3 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address 23 Bit Symbol Read/Write Reset Value Function 0 22 21 20 BA3 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address 15 Bit Symbol Read/Write Reset Value Function 0 14 13 12 MA3 R/W 11 10 9 8 0 0 0 Must be written as 0. 0 0 0 1 7 Bit Symbol Read/Write Reset Value Function 1 6 5 4 MA3 R/W 3 2 1 0 1 1 1 1 1 1 1 CS3 block size 0: The address compare logic uses this address bit. Note: Bits 9-15 in the BMA2 and BMA3 must be written as zeros. The CS2 and CS3 block sizes can vary from 32 Kbytes to 2 Gbytes. However, the TMP1962 supports only 16 Mbytes of external address space. Therefore, bits 9-15 in the BMA2 and BMA3 must be cleared so that A24-A30 of an address will not be masked. Figure 9.2 Base/Mask Address Registers (BMA2 and BMA3) TMP1962-163 2006-02-21 TMP1962C10BXBG Address 0xFFFF_FFFF Starting Address 0xFFFF_0000 Base Address Value (BAn) FFFF 0x0006_0000 0x0005_0000 0x0004_0000 0x0003_0000 0x0002_0000 0x0001_0000 0x0000_0000 64 Kbytes 0x0000_0000 0006 0005 0004 0003 0002 0001 0000 Figure 9.3 Relationships Between Starting Addresses and Base Address Register Values 9.1.2 Base Address and Address Mask Value Calculations * Program the BMA0 register as follows to cause CS0 to be asserted in the 64 Kbytes of address space starting at 0xC000_0000. 31 BA0 C 0 0 0 0 0 16 15 MA0 0 3 0 11000000000000000000000000000011 BMA0 Register Value The BA0 field specifies the upper 16 bits of the starting address, or 0xC000. The MA0 field determines whether the A29-A14 bits of the address should be compared or masked. The A31 and A30 bits are always compared. Bits 15-10 of the MA0 field must be cleared so that the A29-A24 bits are always compared. When the BMA0 register is programmed as shown above, the A31-A16 bits of the address are compared to the value of the BA0 field. Consequently, the 64-Kbyte address range between 0xC000_0000 and 0xC000_FFFF is defined as the CS0 space. TMP1962-164 2006-02-21 TMP1962C10BXBG * Program the BMA2 register as follows to cause CS2 to be asserted in the 1 Mbyte of address space starting at 0x1FD0_0000. 31 BA2 1 F D 0 0 0 16 15 MA2 1 F 0 00011111110100000000000000011111 BMA2 Register Value The BA2 field specifies the upper 16 bits of the starting address, or 0x1FD0. The MA2 field determines whether the A30-A15 bits of the address should be compared or masked. The A31 bit is always compared. Bits 15-5 of the MA2 field must be cleared so that the A30-A20 bits are always compared. When the BMA2 register is programmed as shown above, the A31-A20 bits of the address are compared to the value of the BA2 field. Consequently, the 1-Mbyte address range between 0x1FD0_0000 and 0x1FDF_FFFF is defined as the CS2 space. Note: The TMP1962 does not assert any CSn signal in the following address ranges: 0x1FC_0000 through 0x1FCF_FFFF 0x4000_0000 through 0x400F_FFFF 0xFFFD_6000 through 0xFFFD_FFFF 0xFFFF_6000 through 0xFFFF_DFFF Upon reset, the CS0, CS1 and CS3 spaces are disabled while the CS2 space is enabled and spans the entire 4-GB address space. TMP1962-165 2006-02-21 TMP1962C10BXBG Table 9.1 shows the programmable block sizes for CS0 to CS3. Even if the user has accidentally programmed more than one chip select line to the same area, only one chip select line is driven because of internal line priorities. CS0 has the highest priority, and CS3 the lowest. Example: The starting address of the CS0 space is programmed as 0xC000_0000 with a size of 16 Kbytes. The starting address of the CS1 space is programmed as 0xC000_0000 with a size of 64 Kbytes. CS0 Space CS1 Space 0xC000_FFFF 0xC000_3FFF 0xC000_0000 0xC000_3FFF 0xC000_0000 When an attempt is made to access the overlapping area, the CS0 area is selected. Table 9.1 Supported Block Sizes Size (bytes) CS Space CS0 CS1 CS2 CS3 16 K 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M 16 M TMP1962-166 2006-02-21 TMP1962C10BXBG 9.2 Chip Select/Wait Control Registers The organization of the Chip Select/Wait Control registers is shown in Figure 9.4. Each of these registers consist of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. The B01CS register defines the CS0 and CS1 lines; the B23CS register defines the CS2 and CS3 lines; and the BEXCS register defines the access characteristics for the rest of the address locations. If the user has accidentally programmed more than one chip select line to the same area, only one chip select line is driven because of internal line priorities (CS0 > CS1 > CS2 > CS3 > EXCS). B01CS (0xFFFF_E480), B23CS (0xFFFF_E484), BEXCS (0xFFFF_E488) 31 30 29 B1WCV R/W 0 0 Number of dummy cycles (Write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited 28 27 B1E R/W 0 CS1 enable 0: Disable 1: Enable 26 25 B1RCV R/W 0 24 B01CS (0xFFFFE480) Bit Symbol Read/Write Reset Value Function 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited 23 Bit Symbol Read/Write Reset Value Function 0 B1OM R/W 22 21 20 B1BUS 19 18 B1W R/W 17 16 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Do not use any other value. Number of wait-state cycles (Automatically inserted wait states) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (Externally inserted wait states) 1001: (1+N) WAIT 1011: (3+N) WAIT 1101: (5+N) WAIT 1111: (7+N) WAIT 1000,1010,1100,1110: reserved 15 Bit Symbol Read/Write Reset Value Function 14 13 B0WCV R/W 0 12 11 B0E R/W 10 9 B0RCV R/W 0 8 0 0 CS0 enable 0: Disable 1: Enable 0 Number of dummy cycles (Write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited 7 Bit Symbol Read/Write Reset Value Function 0 B0OM R/W 6 5 4 B0BUS 3 2 B0W R/W 1 0 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Do not use any other value. Number of wait-state cycles (Automatically inserted wait states) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (Externally inserted wait states) 1001: (1+N) WAIT 1011: (3+N) WAIT 1101: (5+N) WAIT 1111: (7+N) WAIT 1000,1010,1100,1110: reserved Figure 9.4 Chip Select/Wait Control Registers (1/3) Note:"Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width. " TMP1962-167 2006-02-21 TMP1962C10BXBG 31 B23CS (0xFFFF_E484) Bit Symbol Read/Write Reset Value Function 30 29 B3WCV R/W 0 28 27 B3E R/W 26 25 B3RCV R/W 0 24 0 0 CS3 enable 0: Disable 1: Enable 0 Number of dummy cycles (Write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited 23 Bit Symbol Read/Write Reset Value Function 0 B3OM R/W 22 21 20 B3BUS 19 18 B3W R/W 17 16 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Do not use any other value. Number of wait-state cycles (Automatically inserted wait states) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (Externally inserted wait states) 1001: (1+N) WAIT 1011: (3+N) WAIT 1101: (5+N) WAIT 1111: (7+N) WAIT 1000,1010,1100,1110: reserved 15 Bit Symbol Read/Write Reset Value Function 14 13 B2WCV R/W 0 12 11 B2E 10 B2M R/W 0 CS2 space select 9 B2RCV 0 8 0 1 CS2 enable 0: Disable 1: Enable 0 Number of dummy cycles (Write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 0: Whole 4-Gbyte 10: No dummy cycle space 11: Setting prohibited 1: CS space 7 Bit Symbol Read/Write Reset Value Function 0 B2OM R/W 6 5 4 B2BUS 3 2 B2W R/W 1 0 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Do not use any other value. Number of wait-state cycles (Automatically inserted wait states) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (Externally inserted wait states) 1001: (1+N) WAIT 1011: (3+N) WAIT 1101: (5+N) WAIT 1111: (7+N) WAIT 1000,1010,1100,1110: reserved Figure 9.4 Chip Select/Wait Control Registers (2/3) Note:"Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width. " TMP1962-168 2006-02-21 TMP1962C10BXBG 15 BEXCS (0xFFFF_E488) Bit Symbol Read/Write Reset Value Function 14 13 R/W 0 12 11 R/W 10 9 BEXRCV R/W 0 8 BEXWCV 0 0 0 Number of dummy cycles (Write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Setting prohibited 7 Bit Symbol Read/Write Reset Value Function 0 BEXOM R/W 6 5 4 BEXBUS 3 2 BEXW R/W 1 0 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Do not use any other value. Number of wait-state cycles (Automatically inserted wait states) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (Externally inserted wait states) 1001: (1+N) WAIT 1011: (3+N) WAIT 1101: (5+N) WAIT 1111: (7+N) WAIT 1000,1010,1100,1110: reserved Figure 9.4 Chip Select/Wait Control Registers (3/3) Note:"Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width. " Both CS1 and CS2 are shared with Port 4 pins. Upon reset, all Port 4 pins are configured as input port pins. To use them as chip select pins, set appropriate bits in the Port 4 Control (P4CR) register and the Port 4 Function (P4FC) register to 1. TMP1962-169 2006-02-21 TMP1962C10BXBG 10. DMA Controller (DMAC) The TMP1962 contains an eight-channel DMA controller. 10.1 Features The TMP1962 DMAC has the following features: (1) Eight independent DMA channels (2) Two types of bus requests, with and without bus snooping (3) Transfer requests: Internal transfer requests: Software initiated External transfer requests: Interrupt signals from on-chip I/O peripherals and external interrupt pins, or request signals from DREQ pins Request signals from DREQ : Level-sensitive mode (memory-to-memory) Edge-triggered mode (memory-to-I/O, I/O-to-memory) (4) Dual-address mode (5) Memory-to-memory, memory-to-I/O, and I/O-to-memory transfers (6) Transfer width: * * Memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the CS/Wait Controller.) I/O peripherals: 8-, 16-, and 32-bit (7) Address pointers can increment, decrement or remain constant. The user can program the bit positions at which address increment or decrement occurs. (8) Fixed channel priority (9) Selectable endian mode TMP1962-170 2006-02-21 TMP1962C10BXBG 10.2 Implementation 10.2.1 On-Chip DMAC Interface Figure 10.1 shows how the DMAC is internally connected with the TX19 core processor and the Interrupt Controller (INTC). DREQ [3:2] DACK [3:2] DACK [7:0] * INTDREQ [7:0] * TX19 Core Processor Bus Grant Interrupt Controller (INTC) (External Requests) External Interrupt On-Chip I/O Peripheral Interrupt Requests DMAC BUSGNT * Bus Request Bus Release Request Bus Grant Acknowledge Control Address Data BUSREQ * BUSREL * HAVEIT * * Internal signals Figure 10.1 DMAC Connections within the TMP1962 The DMAC provides eight independently programmable channels. With each DMA channel, there are two associated signals: a DMA request ( INTDREQn ) and a DMA acknowledge ( DACKn ), where n is a channel number from 0 to 7. INTDREQn is an input to the DMAC coming from the INTC, and DACKn is an output signal from the DMAC going to the INTC. Channels 2 and 3 also accept external DMA requests from the DREQ 2 and DREQ3 pins and send acknowledge signals through the DACK 2 and DACK3 pins. Channel priority is fixed. Channel 0 has the highest priority, and Channel 7 has the lowest priority. The TX19 core processor supports bus snooping. When snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC, so that the DMAC can access the on-chip RAM and ROM connected to the processor. Snooping can be enabled and disabled under software control. The DMAC bus snooping is discussed in Section 10.2.3 in more detail. There are two bus request signals from the DMAC going to the TX19 core processor, SREQ and GREQ. GREQ is a bus request without snooping. SREQ is a bus request with snooping. SREQ always takes precedence over GREQ. TMP1962-171 2006-02-21 TMP1962C10BXBG 10.2.2 DMAC Block The DMAC block diagram is shown in Figure 10.2. Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 31 Source Address Register (SARx) Destination Address Register (DARx) Byte Count Register (BCRx) Channel Control Register (CCRx) Channel Status Register (CSRx) DMA Transfer Control Register (DTCRx) (x = 0 to 7) 0 DMA Control Register (DCR) Request Select Register (RSR) Data Holding Register (DHR) Figure 10.2 DMAC Block Diagram 10.2.3 Bus Snooping The TX19 core processor supports snoop operations. If snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC. Because the DMAC takes control of the processor data bus, the TX19 stops operating during snoop operations until the DMAC relinquishes the bus to the processor. Snooping allows the DMAC to access the on-chip RAM and ROM, and thus to use them as a DMA source or destination device. If snooping is disabled, the DMAC cannot access the on-chip RAM and ROM. However, regardless of whether snooping is enabled or disabled, the DMAC assumes mastership of the TMP1962 on-chip bus (G-Bus) during DMA transfers. Therefore, as long as DMA transfers are in progress, the TX19 core processor cannot access memory or I/O peripherals via the G-Bus; any attempt to do so causes the processor pipeline to stall. Note: If snooping is disabled, the TX19 core processor does not grant mastership of the processor data bus to the DMAC. Therefore, if the on-chip RAM or ROM is specified as a source or destination for DMA transfers, a DMA acknowledge signal will never be returned, causing bus lockup. TMP1962-172 2006-02-21 TMP1962C10BXBG 10.3 Register Description The DMAC has fifty-one 32-bit registers. The DMAC register map is shown in Table 10.1. Table 10.1 DMAC Registers (1/2) Address 0xFFFF_E200 0xFFFF_E204 0xFFFF_E208 0xFFFF_E20C 0xFFFF_E210 0xFFFF_E218 0xFFFF_E220 0xFFFF_E224 0xFFFF_E228 0xFFFF_E22C 0xFFFF_E230 0xFFFF_E238 0xFFFF_E240 0xFFFF_E244 0xFFFF_E248 0xFFFF_E24C 0xFFFF_E250 0xFFFF_E258 0xFFFF_E260 0xFFFF_E264 0xFFFF_E268 0xFFFF_E26C 0xFFFF_E270 0xFFFF_E278 0xFFFF_E280 0xFFFF_E284 0xFFFF_E288 0xFFFF_E28C 0xFFFF_E290 0xFFFF_E298 0xFFFF_E2A0 0xFFFF_E2A4 0xFFFF_E2A8 0xFFFF_E2AC 0xFFFF_E2B0 0xFFFF_E2B8 0xFFFF_E2C0 0xFFFF_E2C4 0xFFFF_E2C8 0xFFFF_E2CC 0xFFFF_E2D0 0xFFFF_E2D8 Symbol CCR0 CSR0 SAR0 DAR0 BCR0 DTCR0 CCR1 CSR1 SAR1 DAR1 BCR1 DTCR1 CCR2 CSR2 SAR2 DAR2 BCR2 DTCR2 CCR3 CSR3 SAR3 DAR3 BCR3 DTCR3 CCR4 CSR4 SAR4 DAR4 BCR4 DTCR4 CCR5 CSR5 SAR5 DAR5 BCR5 DTCR5 CCR6 CSR6 SAR6 DAR6 BCR6 DTCR6 Register Name Channel Control Register (Ch. 0) Channel Status Register (Ch. 0) Source Address Register (Ch. 0) Destination Address Register (Ch. 0) Byte Count Register (Ch. 0) DMA Transfer Control Register (Ch. 0) Channel Control Register (Ch. 1) Channel Status Register (Ch. 1) Source Address Register (Ch. 1) Destination Address Register (Ch. 1) Byte Count Register (Ch. 1) DMA Transfer Control Register (Ch. 1) Channel Control Register (Ch. 2) Channel Status Register (Ch. 2) Source Address Register (Ch. 2) Destination Address Register (Ch. 2) Byte Count Register (Ch. 2) DMA Transfer Control Register (Ch. 2) Channel Control Register (Ch. 3) Channel Status Register (Ch. 3) Source Address Register (Ch. 3) Destination Address Register (Ch. 3) Byte Count Register (Ch. 3) DMA Transfer Control Register (Ch. 3) Channel Control Register (Ch. 4) Channel Status Register (Ch. 4) Source Address Register (Ch. 4) Destination Address Register (Ch. 4) Byte Count Register (Ch. 4) DMA Transfer Control Register (Ch. 4) Channel Control Register (Ch. 5) Channel Status Register (Ch. 5) Source Address Register (Ch. 5) Destination Address Register (Ch. 5) Byte Count Register (Ch. 5) DMA Transfer Control Register (Ch. 5) Channel Control Register (Ch. 6) Channel Status Register (Ch. 6) Source Address Register (Ch. 6) Destination Address Register (Ch. 6) Byte Count Register (Ch. 6) DMA Transfer Control Register (Ch. 6) TMP1962-173 2006-02-21 TMP1962C10BXBG Figure 10.2 DMAC Registers (2/2) 0xFFFF_E2E0 0xFFFF_E2E4 0xFFFF_E2E8 0xFFFF_E2EC 0xFFFF_E2F0 0xFFFF_E2F8 0xFFFF_E300 0xFFFF_E304 0xFFFF_E30C CCR7 CSR7 SAR7 DAR7 BCR7 DTCR7 DCR RSR DHR Channel Control Register (Ch. 7) Channel Status Register (Ch. 7) Source Address Register (Ch. 7) Destination Address Register (Ch. 7) Byte Count Register (Ch. 7) DMA Transfer Control Register (Ch. 7) DMA Control Register (DMAC) Request Select Register (DMAC) Data Holding Register (DMAC) TMP1962-174 2006-02-21 TMP1962C10BXBG 10.3.1 31 Rstall W 30 DMA Control Register (DCR) 16 : Read/Write 15 7 Rst7 Rst6 Rst5 Rst4 Rst3 Rst2 Rst1 0 Rst0 : Read/Write W Bits 31 Mnemonic Rstall Field Name Reset All Description Performs a software reset of the DMAC. When the Rstall bit is set to 1, all the DMAC internal registers are initialized to their reset values. Any transfer requests are removed and all the eight DMA channels are put in Idle state. 0: Don't care 1: Resets the DMAC. 7 Rst7 Reset 7 Performs a software reset of DMAC Channel 7. When the Rst7 bit is set to 1, all the DMAC Channel 7 internal registers and the RSR Channel 7 bit are initialized to their reset values. Any transfer requests for Channel 7 are removed and Channel 7 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 7. 6 Rst6 Reset 6 Performs a software reset of DMAC Channel 6. When the Rst6 bit is set to 1, all the DMAC Channel 6 internal registers and the RSR Channel 6 bit are initialized to their reset values. Any transfer requests for Channel 6 are removed and Channel 6 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 6. 5 Rst5 Reset 5 Performs a software reset of DMAC Channel 5. When the Rst5 bit is set to 1, all the DMAC Channel 5 internal registers and the RSR Channel 5 bit are initialized to their reset values. Any transfer requests for Channel 5 are removed and Channel 5 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 5. 4 Rst4 Reset 4 Performs a software reset of DMAC Channel 4. When the Rst4 bit is set to 1, all the DMAC Channel 4 internal registers and the RSR Channel 4 bit are initialized to their reset values. Any transfer requests for Channel 4 are removed and Channel 4 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 4. 3 Rst3 Reset 3 Performs a software reset of DMAC Channel 3. When the Rst3 bit is set to 1, all the DMAC Channel 3 internal registers and the RSR Channel 3 bit are initialized to their reset values. Any transfer requests for Channel 3 are removed and Channel 3 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 3. TMP1962-175 2006-02-21 TMP1962C10BXBG Bits 2 Mnemonic Rst2 Field Name Reset 2 Description Performs a software reset of DMAC Channel 2. When the Rst2 bit is set to 1, all the DMAC Channel 2 internal registers and the RSR Channel 2 bit are initialized to their reset values. Any transfer requests for Channel 2 are removed and Channel 2 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 2. 1 Rst1 Reset 1 Performs a software reset of DMAC Channel 1. When the Rst1 bit is set to 1, all the DMAC Channel 1 internal registers and the RSR Channel 1 bit are initialized to their reset values. Any transfer requests for Channel 1 are removed and Channel 1 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 1. 0 Rst0 Reset 0 Performs a software reset of DMAC Channel 0. When the Rst0 bit is set to 1, all the DMAC Channel 0 internal registers and the RSR Channel 0 bit are initialized to their reset values. Any transfer requests for Channel 0 are removed and Channel 0 is put in Idle state. 0: Don't care 1: Resets DMAC Channel 0. Figure 10.3 DMA Control Register (DCR) Note 1: If the software reset command is written to the DCR register immediately after the completion of the last transfer cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software reset only initializes channel registers and other settings. Note 2: Do not issue a software reset command to the DCR register via a DMA transfer. TMP1962-176 2006-02-21 TMP1962C10BXBG 10.3.2 31 Str W 30 Channel Control Registers (CCRn) 25 0 24 W 23 NIEn R/W 1 22 AbIEn R/W 1 6 DIO R/W 0 21 R/W 1 5 DAC R/W 00 20 R/W 0 4 19 R/W 0 3 TrSiz R/W 00 18 R/W 0 2 17 Big R/W 1 1 DPS R/W 00 : Read/Write : Reset Value 16 R/W : Read/Write 0 0 : Reset Value 15 R/W 0 14 ExR R/W 0 13 PosE R/W 0 12 Lev R/W 0 11 10 9 SIO R/W 0 8 SAC R/W 00 7 SReq RelEn R/W 0 R/W 0 Bits 31 Mnemonic Str Field Name Channel Start Start (Reset value: -) Description Enables a DMA channel. Setting this bit puts the DMA channel in Ready state. DMA transfer starts as soon as a transfer request is received. Only a write of 1 is valid, and a write of 0 has no effect on this bit. A 0 is returned on read. 1: Enables a DMA channel. 24 23 NIEn (Reserved) Normal Completion Interrupt Enable This bit is reserved and must be written as 0. Normal Completion Interrupt Enable (Reset value: 1) 1: Enables an interrupt when the channel finishes a transfer without an error condition. 0: Does not enable an interrupt when the channel finishes a transfer without an error condition. 22 AbIEn Abnormal Termination Interrupt Enable Abnormal Completion Interrupt Enable (Reset value: 1) 1: Enables an interrupt when the channel encounters a transfer error. 0: Does not enable an interrupt when the channel encounters a transfer error. 21 20 19 18 17 Big (Reserved) (Reserved) (Reserved) (Reserved) Big-Endian This bit is reserved and reset to 1, but it must be written as 0. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. Big Endian (Reset value: 1) 1: The DMA channel operates in big-endian mode. 0: The DMA channel operates in little-endian mode. 16 15 14 ExR (Reserved) (Reserved) External Request Mode This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. External Request Mode (Reset value: 0) Selects a transfer request mode. 1: External transfer requests (interrupt-driven or DREQ-driven) 0: Internal transfer requests (software-initiated) 13 PosE Positive Edge Positive Edge (Reset value: 0) Defines the polarity of the internal DMA request signal (INTDREQn or DREQn) for the channel. This bit is valid for external transfer requests (i.e., when ExR = 1), and has no effect on internal transfer requests (i.e., when ExR = 0). The PosE bit must always be cleared because INTDREQn and DREQn are low-active signals. 1: Setting prohibited 0: INTDREQn and DREQn are configured as falling-edge triggered or low-level sensitive. DACKn is low active. Figure 10.4 Channel Control Registers (CCRn) (1/3) TMP1962-177 2006-02-21 TMP1962C10BXBG Bits 12 Mnemonic Lev Field Name Level Mode Description Level Mode (Reset value: 0) Specifies whether external transfer requests are level-sensitive or edge-triggered. This bit is valid for external transfer requests (i.e., when ExR = 1), and has no effect on internal transfer requests (i.e., when ExR = 0). The Lev bit must always be set to 1 because INTDREQn is low-active signals. The Lev bit determines how DREQn is recognized, as follows: 1: Level mode. A specified level (if PosE = 0, low level) of DREQn is recognized as a data transfer request. 0: Edge mode. A specified transition (if PosE = 0, falling edge) of DREQn is recognized as a data transfer request. 11 SReq Snoop Request Snoop Request (Reset value: 0) Controls whether or not to request bus mastership with snooping. If set, the TX19 core processor's snoop function becomes valid, allowing the DMAC to use the processor's data bus. If cleared, the snoop function is disabled. 1: The snoop function is enabled (i.e., SREQ is used as a bus request signal). 0: The snoop function is disabled (i.e., GREQ is used as a bus request signal). 10 RelEn Bus Release Request Enable Release Request Enable (Reset value: 0) Controls whether or not to respond to the bus release request signal from the TX19 core processor. This bit is valid when the DMAC uses GREQ as a bus request signal. This bit has no meaning or effect when the DMAC uses SREQ as a bus request signal because, in that case, the TX19 core processor does not have the capability to generate a bus release request signal. 1: The DMAC will respond to the bus release request signal from the TX19 core processor, if it has control of the bus. The DMAC will relinquish the bus when the current DMA bus cycle completes. 0: The DMAC will ignore the bus release request signal from the TX19 core processor. 9 SIO I/O Source Source Type: I/O (Reset value: 0) Specifies the type of the source device. 1: I/O device 0: Memory 8:7 SAC Source Address Count Source Address Count (Reset value: 00) Selects the manner in which the source address changes after each cycle. 1x: Fixed (remains unchanged) 01: Decremented 00: Incremented 6 DIO I/O Destination Destination Type: I/O (Reset value: 0) Specifies the type of the destination device. 1: I/O device 0: Memory 5:4 DAC Destination Address Count Destination Address Count (Reset value: 00) Selects the manner in which the destination address changes after each cycle. 1x: Fixed (remains unchanged) 01: Decremented 00: Incremented Figure 10.4 Channel Control Registers (CCRn) (2/3) TMP1962-178 2006-02-21 TMP1962C10BXBG Bits 3:2 Mnemonic TrSiz Field Name Transfer Size Description Transfer Size (Reset value: 00) Specifies the amount of data to be transferred in response to a DMA request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1:0 DPS Device Port Size Device Port Size (Reset value: 00) Specifies the port size of a source or destination I/O device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) Figure 10.4 Channel Control Registers (CCRn) (3/3) Note 1: The CCRn register must be programmed before placing the DMAC in Ready state. Note 2: To access on-chip peripherals or to perform a DMA transfer in response to a request issued through a DREQ pin, the transfer size (TrSiz) must be equal to the device port size (DPS). Note 3: The DPS field has no meaning or effect on memory-to-memory transfers. 10.3.3 31 Request Select Register (RSR) 16 0 : Read/Write : Reset Value 15 0 3 2 0 ReqS3 ReqS2 R/W 0 0 0 0 0 R/W 0 0 0 : Read/Write : Reset Value Bits 3 Mnemonic ReqS3 Field Name Request Select (Ch. 3) Description Request Select (Reset value: 0) Selects the type of an external transfer request enabled for DMA Channel 3. 1: Request from the DREQ3 pin. 0: Request from the Interrupt Controller (INTC). 2 ReqS2 Request Select (Ch. 2) Request Select (Reset value: 0) Selects the type of an external transfer request enabled for DMA Channel 2. 1: Request from the DREQ2 pin. 0: Request from the Interrupt Controller (INTC). Note: Bits 0, 1, and 4 to 7 of the RSR must be set to 0. Figure 10.5 Request Select Register (RSR) TMP1962-179 2006-02-21 TMP1962C10BXBG 10.3.4 31 Act R 0 15 Channel Status Registers (CSRn) 23 NC R/W 0 22 AbC R/W 0 21 R/W 0 20 BES R 0 19 BED R 0 3 0 18 Conf R 0 2 R/W 000 : Read/Write : Reset Value 0 17 00 : Read/Write : Reset Value 16 Bits 31 Mnemonic Act Field Name Channel Active Description Channel Active (Reset value: 0) Indicates whether or not the DMA channel is in Ready state. 1: The DMA channel is in Ready state. 0: The DMA channel is not in Ready state. 23 NC Normal Completion Normal Completion (Reset value: 0) If set, the DMA channel has terminated by normal completion. If the NIEn bit in the CCRn is set, an interrupt is generated. The NC bit is cleared by writing a 0 to it. Clearing the NC bit causes the interrupt to be cleared. The NC bit must be cleared prior to starting the next transfer. An attempt to set the Str bit in the CCRn when NC = 1 will cause an error. A write of 1 has no effect on this bit. 1: The DMA channel has terminated by normal completion. 0: The DMA channel has not terminated by normal completion. 22 AbC Abnormal Completion Abnormal Completion (Reset value: 0) If set, the DMA channel has terminated with an error. If the AbIEn bit in the CCRn is set, an interrupt is generated. The AbC bit is cleared by writing a 0 to it. Clearing the AbC bit causes the interrupt to be cleared and the BES, BED and Conf bits to be also cleared. The AbC bit must be cleared prior to starting the next transfer. An attempt to set the Str bit in the CCRn when AbC = 1 will cause an error. A write of 1 has no effect on this bit. 1: The DMA channel has terminated with an error. 0: The DMA channel has not terminated with an error. 21 20 BES (Reserved) Source Bus Error This bit is reserved and must be written as 0. Source Bus Error (Reset value: 0) 1: A bus error has occurred during the source read cycle. 0: A bus error has not occurred during the source read cycle. 19 BED Destination Bus Error Destination Bus Error (Reset value: 0) 1: A bus error has occurred during the destination write cycle. 0: A bus error has not occurred during the destination write cycle. 18 Conf Configuration Error Configuration Error (Reset value: 0) 1: A configuration error is present. 0: No configuration error is present. 2:0 (Reserved) These bits are reserved and must be written as 0s. Figure 10.6 Channel Status Registers (CSRn) TMP1962-180 2006-02-21 TMP1962C10BXBG 10.3.5 31 Source Address Registers (SARn) 16 SAddr R/W : Read/Write : Reset Value 0 SAddr R/W : Read/Write : Reset Value 15 Bits 31 : 0 Mnemonic SAddr Field Name Source Address Description Source Address (Reset value: -) Contains the physical address of the source device. The address changes as programmed in the SAC and TrSiz fields in the CCRn and the SACM field in the DTCRn. Figure 10.7 Source Address Registers (SARn) TMP1962-181 2006-02-21 TMP1962C10BXBG 10.3.6 31 Destination Address Registers (DARn) 16 DAddr R/W : Read/Write : Reset Value 0 DAddr R/W : Read/Write : Reset Value 15 Bits 31 : 0 Mnemonic DAddr Field Name Destination Address Description Destination Address (Reset value: -) Contains the physical address of the destination device. The address changes as programmed in the DAC and TrSiz fields in the CCRn and the DACM field in the DTCRn. Figure 10.8 Destination Address Registers (DARn) TMP1962-182 2006-02-21 TMP1962C10BXBG 10.3.7 31 Byte Count Registers (BCRn) 24 0 23 BC R/W : Read/Write : Reset Value 0 BC R/W : Read/Write : Reset Value 16 15 Bits 23 : 0 Mnemonic BC Field Name Byte Count Description Byte Count (Reset value: -) Contains the number of bytes left to transfer on a DMA channel. The count is decremented by 1, 2 or 4 (as determined by the TrSiz field in the CCRn register) for each successful transfer. Figure 10.9 Byte Count Registers (BCRn) TMP1962-183 2006-02-21 TMP1962C10BXBG 10.3.8 31 DMA Transfer Control Registers (DTCRn) 16 0 : Read/Write : Reset Value 15 6 5 DACM R/W 000 3 2 SACM 0 : Read/Write 000 : Reset Value Bits 5:3 Mnemonic DACM Field Name Destination Address Count Mode Description Destination Address Count Mode Selects the manner in which the destination address is incremented or decremented. 000: Counting begins with bit 0 of the DARn. 001: Counting begins with bit 4 of the DARn. 010: Counting begins with bit 8 of the DARn. 011: Counting begins with bit 12 of the DARn. 100: Counting begins with bit 16 of the DARn. 101: Reserved 110: Reserved 111: Reserved 2:0 SACM Source Address Count Mode Source Address Count Mode Selects the manner in which the source address is incremented or decremented. 000: Counting begins with bit 0 of the SARn. 001: Counting begins with bit 4 of the SARn. 010: Counting begins with bit 8 of the SARn. 011: Counting begins with bit 12 of the SARn. 100: Counting begins with bit 16 of the SARn. 101: Reserved 110: Reserved 111: Reserved Figure 10.10 DMA Transfer Control Registers (DTCRn) TMP1962-184 2006-02-21 TMP1962C10BXBG 10.3.9 31 Data Holding Register (DHR) 16 DOT R/W : Read/Write : Reset Value 0 DOT R/W : Read/Write : Reset Value 15 Bits 31 : 0 Mnemonic DOT Field Name Data on Transfer Description Data on Transfer (Reset value: -) Contains data read from the source address during a dual-address operation. Figure 10.11 Data Holding Register (DHR) TMP1962-185 2006-02-21 TMP1962C10BXBG 10.4 Operation This section describes the operation of the DMAC. 10.4.1 Overview The DMAC is a high-speed 32-bit DMA controller used to move quickly large blocks of data between I/O peripherals and memory without intervention of the TX19 core processor. (1) Devices supported for the source and destination The DMAC handles data transfers from memory to memory, and between memory and I/O peripherals. The device from which data is transferred is referred to as a source device, and the device to which data is transferred is referred to as a destination device. Both memory and I/O peripherals can be a source or destination device. The DMAC supports data transfers from memory to I/O peripherals, from I/O peripherals to memory, and from memory to memory, but not from I/O peripherals to I/O peripherals. DMA protocols for memory and I/O peripherals differ in that when accessing an I/O peripheral, the DMAC asserts the DACKn (n = channel number) signal to indicate that data is being transferred in response to a previous transfer request. Because each DMA channel has only one DACKn signal, the DMAC cannot handle data transfers between two I/O peripherals. Interrupt requests can be programmed to be a trigger to initiate a DMA process instead of requesting an interrupt to the TX19 core processor. If so programmed, the Interrupt Controller (INTC) forwards a DMA request to the DMAC (see "Interrupts"). The DMA request coming from the INTC is cleared when the INTC receives a DACKn from the DMAC. Consequently, a DMA request for a transfer to/from an I/O peripheral is cleared after each DMA bus cycle (i.e., every time the number of bytes programmed into the CCRn.TrSiz field is transferred). On the other hand, during memory-to-memory transfer, the DACKn signal is not asserted until the byte count register (BCRn) reaches zero. Therefore, memory-to-memory transfer can continuously move large blocks of data in response to a single DMA request. For example, data transfers between the TMP1962 on-chip peripheral and on- or off-chip memory is discontinued after every DMA bus cycle. Nonetheless, until the BCRn register reaches zero, the DMAC remains in Ready state to wait for the next transfer request. (2) Exchanging bus mastership (bus arbitration) In response to a DMA request, the DMAC issues a bus request to the TX19 core processor. When the DMAC receives a bus grant signal from the TX19 core processor, it assumes bus mastership to service the DMA request. There are two bus request signals from the DMAC going to the TX19 core processor. One is a bus request without snooping (GREQ), and the other is a bus request with snooping (SREQ). The SReq bit in the CCRn register is used to select a bus request signal to use for each DMA channel. While the DMAC has control of the bus, the TX19 core processor may issue a bus release request to the DMAC. The RelEn bit of the CCRn register controls whether to honor this request on a channel-by-channel basis. This setting has a meaning only when a DMA channel uses GREQ (i.e., a bus request without snooping). It has no meaning or effect when a DMA channel uses SREQ (i.e., a bus request with snooping) because, in this case, the TX19 core processor does not have the capability to generate a bus release request. TMP1962-186 2006-02-21 TMP1962C10BXBG The DMAC relinquishes the bus to the TX19 core processor when there is no pending DMA request to be serviced. Note 1: The NMI interrupt is left pending while the DMAC has control of the bus. Note 2: Do not place the TMP1962 in Halt power-down mode while the DMAC is operating. (3) Transfer request generation Each DMA channel supports two types of request generation method: internal and external. Internal requests are those generated within the DMAC. The DMA channel is started as soon as the Str bit in the CCRn register is set. The channel immediately requests the bus and begins transferring data. If a channel is programmed for external request and the Str bit is set, the INTDREQn signal asserted by the Interrupt Controller or the DREQn signal asserted by the external device causes the channel to request the bus and begin a transfer. The DMAC can be programmed to recognize a transfer request either with the low level of the INTDREQn signal or with the falling edge or low level of the DREQn signal. (4) Data transfer modes The TMP1962 DMAC supports dual-address transfers, but not single-address transfers. The dual-address mode allows data to be transferred from memory to memory and between memory and an I/O peripheral. In this mode, the DMAC explicitly addresses both the source and destination devices. The DMAC also generates a DACKn signal when accessing an I/O peripheral. In dual-address mode, a transfer takes place in two DMA bus cycles: a source read cycle and a destination write cycle. In the source read cycle, the data being transferred is read from the source address and put into the DMAC internal Data Holding Register (DHR). In the destination write cycle, the DMAC writes data in the DHR to a destination address. (5) DMA channel operation The DMAC has eight independent DMA channels, 0 to 7. Setting the Start (Str) bit in the CCRn (n = 0-7) enables a particular channel and puts it in Ready state. When a DMA request is detected in any of the channels in Ready state, the DMAC arbitrates for the bus and begins a transfer. When no DMA request is pending, the DMAC relinquishes the bus to the TX19 core processor and returns to Ready state. The channel can terminate by normal completion or from an error of a bus cycle. When a channel terminates, that channel is put in Idle state. Interrupts can be generated by error termination or by normal channel termination. Figure 10.12 shows general state transitions of a DMA channel. The DMAC gives up bus mastership. Ready Start The DMAC gives up bus mastership. Idle The DMAC assumes bus mastership. Transfer done Transfer The DMAC assumes bus mastership. Figure 10.12 DMA Channel State Transitions TMP1962-187 2006-02-21 TMP1962C10BXBG (6) Summary of transfer modes The DMAC can perform data transfers as follows according to the combination of mode settings. Transfer Request Internal External Edge/Level Low Level ( INTDREQn ) Low Level ( DREQn ) Address Mode Data Flow Memory-to-memory Memory-to-memory Memory-to-I/O I/O-to-memory Memory-to-memory Memory-to-I/O I/O-to-memory Dual External Falling Edge ( DREQn ) (7) Address change options Address pointers can increment, decrement or remain constant. The SAC and DAC fields in the CCRn respectively select address change directions for the Source Address Register (SARn) and the Destination Address Register (DARn). While memory addresses can be programmed to increment, decrement or remain constant, I/O addresses must be programmed to remain constant. When an I/O peripheral is selected as the source or destination device, the SAC or DAC field in the CCRn must be set to 1x (address fixed). The SACM and DACM fields in the DTCRn provide options to program bit positions at which the source and destination addresses are incremented or decremented after each transfer. The bit position can be bit 0, 4, 8, 12 or 16. Use of bit 0 is the regular increment/decrement mode in which the address changes by 1, 2 or 4, according to the source or destination size. Two examples of how other increment/decrement modes affect address changes are shown below. Example 1: When address bit 0 is selected in the SACM field and address bit 4 is selected in the DACM field SAC: DAC: TrSiz: Source address: Destination address: SACM: DACM: Programmed to increment the source address Programmed to increment the destination address Programmed to a transfer size of 32 bits 0xA000_1000 0xB000_0000 000 Bit 0 is the source address bit at which address increment occurs. 001 Bit 4 is the destination address bit at which address increment occurs. Destination 0xB000_0000 0xB000_0010 0xB000_0020 0xB000_0030 ... 1st transfer 2nd transfer 3rd transfer 4th transfer Source 0xA000_1000 0xA000_1001 0xA000_1002 0xA000_1003 ... TMP1962-188 2006-02-21 TMP1962C10BXBG Example 2: When address bit 8 is selected in the SACM field and address bit 0 is selected in the DACM field SAC: DAC: TrSiz: Source address: Destination address: SACM: DACM: Programmed to decrement the address Programmed to decrement the address Programmed to a transfer size of 16 bits 0xA000_1000 0xB000_0000 010 Bit 8 is the source address bit at which address decrement occurs. 000 Bit 0 is the destination address bit at which address decrement occurs. Destination 0xB000_0000 0xAFFF_FFFE 0xAFFF_FFFC 0xAFFF_FFFA ... 1st transfer 2nd transfer 3rd transfer 4th transfer Source 0xA000_1000 0x9FFF_FF00 0x9FFF_FE00 0x9FFF_FD00 ... 10.4.2 Transfer Request Generation A DMA request must be issued for the DMAC to initiate a data transfer. Each DMA channel in the DMAC supports two types of request generation method: internal and external. In either request generation mode, once a DMA channel is started, a DMA request causes the DMAC to arbitrate for the bus and begin transferring data. * Internal request generation A channel is programmed for internal request by clearing the ExR bit in the CCRn. In internal request generation mode, a transfer request is generated as soon as the Str bit in the CCRn is set. An internally generated request keeps a transfer request pending until the transfer is complete. If no transition to a higher-priority DMA channel or a bus master occurs, the channel will use 100% of the available bus bandwidth to transfer all data continuously. Internally generated requests support only memory-to-memory transfer. * External request generation A channel is programmed for external request by setting the ExR bit in the CCRn. In external request generation mode, setting the Str bit in the CCRn puts the channel in Ready state. While in Ready state, assertion of the INTDREQn signal (where n is the channel number) coming from the Interrupt Controller (INTC), or the DREQn signal coming from an external device, causes a transfer request to be generated. Externally generated requests support data transfers from memory to memory and between memory and an I/O peripheral. The TMP1962 can recognize a transfer request with the low level of INTDREQn or the falling edge or low level of DREQn . The transfer size, i.e., the amount of data to be transferred in response to a transfer request, is programmed in the TrSiz field in the CCRn. The transfer size can be 32 bits, 16 bits or 8 bits. Details of transfer request generation by INTDREQn and DREQn are described below. TMP1962-189 2006-02-21 TMP1962C10BXBG (1) Transfer request coming from the INTC A transfer request is removed by assertion of the DACKn signal (where n is the channel number). DACKn is asserted: 1) when an I/O peripheral bus cycle has completed, and 2) when the Byte Count Register (BCRn) has reached zero in memory-to-memory transfer. Consequently, a memory-to-I/O or I/O-to-memory transfer request terminates after one DMA bus cycle completes, whereas memory-to-memory transfer can continuously move large blocks of data in response to a single DMA request. The INTC might clear INTDREQn before the DMAC accepts it and begins a data transfer. It must be noted that, even if that happens, a DMA bus cycle might be executed after the interrupt request has been cleared. (2) Transfer request coming from an external device In Edge mode, each transfer request requires the deassertion and assertion of the DREQn signal to produce an effective edge. In Level mode, a continuous transfer request can be made by holding an effective level. Memory-to-memory transfer supports Low Level-Sensitive mode only. I/O-to-memory transfer supports Falling Edge-Sensitive mode only. * Level mode In Level mode, the DMAC samples the DREQn signal on the rising edge of the internal system clock. If DREQn is sampled low when the corresponding channel is in Ready state, the DMAC starts transferring data. To detect the low level of DREQn , clear the PosE bit (bit 13) of the CCRn register to 0. The DACKn signal is also low active. Once the external device has asserted DREQn , it must be held low until DACKn is asserted. If DREQn is deasserted before DACKn is asserted, the DMAC may not recognize the transfer request. If DREQn is not sampled low, the DMAC assumes that there is no transfer request for the channel and starts transferring data for another channel or relinquishes the bus, entering Ready state. The quantity of data transferred with a single transfer request is specified in the TrSiz field (bits 3 and 2) of the CCRn register. DREQn A [31:1] Data Transfer DACKn Figure 10.13 Transfer Request Timing (Level Mode) TMP1962-190 2006-02-21 TMP1962C10BXBG * Edge mode In Edge mode, the DMAC is driven by the falling edge of the DREQn signal. If the DMAC detects the falling edge of DREQn on the rising edge of the internal system clock (samples DREQn high on the previous system clock edge and low on the current edge) when the corresponding channel is in Ready state, the DMAC assumes that there is a transfer request on the channel and starts transferring data. To detect the falling edge of DREQn, clear the PosE bit (bit 13) and Lev bit (bit 12) of the CCRn register to 0. The DACKn signal is low active. After asserting the DACKn signal, the DMAC transfers next data if it detects another falling edge of DREQn. If the DMAC does not detect a falling edge of DREQn after asserting DACKn, it assumes that there is no transfer request for the channel and starts transferring data for another channel or relinquishes the bus, entering Ready state. The quantity of data transferred with a single transfer request is specified in the TrSiz field (bits 3 and 2) of the CCRn register. DREQn A[ 31:1] Data Transfer Data Transfer DACKn Figure 10.14 Transfer Request Timing (Edge Mode) TMP1962-191 2006-02-21 TMP1962C10BXBG 10.4.3 DMA Address Modes DMA transfer is generally performed in either of two address modes: dual-address mode and single-address mode. In dual-address mode, both the source and destination devices are explicitly addressed. In single-address mode, only either the source device or the destination device is explicitly addressed. The TMP1962, however, supports dual-address mode only. In dual-address mode, two bus transfers occur: a read from the source device, and a write to the destination device. In the source read cycle, data is read from the source address and placed in the DMAC internal Data Holding Register (DHR). Then, in the destination write cycle, the data held in the DHR is written to the destination address. DMAC Source Device Address Address Bus (1) (2) Data Data Bus (2) (1) Destination Device Figure 10.15 Dual-Address Transfer Mode The transfer size programmed into the CCRn.TrSiz field determines the amount of data that is transferred from a source device to a destination device in response to a DMA request. The transfer size can be 32 bits, 16 bits or 8 bits. The internal DHR is a 32-bit register that serves as a buffer for the data being transferred from a source device to a destination device during dual-address mode. Memory accesses occur in a manner to fulfill the CCRn.TrSiz setting. Remember that the CS/Wait Controller supports either 16-bit or 8-bit bus accesses for external memory. If the DMA transfer size is programmed to 32 bits in CCRn.TrSiz, DMA read and write cycles each take up to four bus cycles to complete. A 16-bit data bus, as programmed in the CS/Wait Controller, requires two independent bus cycles to complete a 32-bit transfer. Likewise, an 8-bit data bus requires four independent bus cycles to complete a 32-bit transfer. TMP1962-192 2006-02-21 TMP1962C10BXBG Memory-to-I/O and I/O-to-memory DMA transfers are governed by the setting of the CCRn.DPS field in addition to the setting of CCRn.TrSiz. The DPS field defines the port size of a source or destination I/O peripheral. The I/O port size can be 32 bits, 16 bits or 8 bits. If the transfer size is equal to the I/O port size, an I/O access takes a single read or single write cycle. If the I/O port size is less than the programmed transfer size, the internal 32-bit DHR serves as a buffer for the data being transferred. For example, assume that the transfer size is programmed to 32 bits. If the source I/O port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles occur, followed by a 32-bit write cycle. (If the destination is an external memory with a 16-bit data bus, the write cycle takes two bus cycles.) The 32 bits of data are buffered in the DHR until the destination write cycle occurs. Source and destination addresses can be programmed to increment or decrement after each transfer. The SARn and DARn change, if so programmed, after each data transfer, depending on the transfer size, i.e., the programmed TrSiz value. The BRCn is decremented by TrSiz for each data transfer. It is forbidden to program the device port size (DPS) to a value greater than the DMA transfer size (TrSiz). The relationships between TrSiz and DPS are summarized below. Table 10.2 DMA Transfer Sizes and Device Port Sizes (in Dual-Address Mode) TrSiz 0x (32 bits) 0x (32 bits) 0x (32 bits) 10 (16 bits) 10 (16 bits) 10 (16 bits) 11 (8 bits) 11 (8 bits) 11 (8 bits) DPS 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) Number of I/O Bus Cycles 1 2 4 Setting prohibited 1 2 Setting prohibited Setting prohibited 1 TMP1962-193 2006-02-21 TMP1962C10BXBG 10.4.4 DMA Channel Operation Each DMA channel is started by setting the Str bit in the CCRn to 1. Once started, the DMAC checks the channel setups for configuration errors. If no configuration error is present, the channel enters Ready state. When a DMA request is detected while in Ready state, the DMAC arbitrates for the bus and begins transferring data. The channel can terminate by normal completion or from an error. The state of termination is indicated in the CSRn. Channel startup A DMA channel is started by setting the Str bit in the CCRn. Once started, the DMAC checks the channel setups for configuration errors. If a configuration error is detected, the channel terminates abnormally. If no configuration error is present, the channel enters Ready state. Once a channel enters Ready state, the Act bit in the CSRn is set to 1. If the channel is programmed for internal requests, the channel requests the bus and starts transferring data immediately. If the channel is programmed for external requests, INTDREQn or DREQn must be asserted before the channel requests the bus. Channel termination A DMA channel can terminate by normal completion or from an error. The status of a DMA operation can be determined by reading the CSRn. A channel terminates abnormally if an attempt is made to set the Str bit in the CCRn when the NC or AbC bit in the CSRn is set. Normal termination A DMA channel terminates by normal completion in the following case. Normal completion always occurs at the boundary of transfers programmed into the CCRn.TrSize field. * Data transfers have terminated, with the BCRn decremented to 0. Abnormal termination The paragraphs that follow summarize the cases in which a DMA channel terminates from an error. * Configuration errors A configuration error results when the channel initialization contains inconsistencies or errors. A configuration error is reported before any data transfer takes place; therefore, in case of a configuration error, the SARn, DARn and BCRn remain unaltered. When a DMA channel has terminated from a configuration error, the AbC and Conf bits in the CSRn are set. A configuration error occurs for the following cases: * * Both the CCRn.SIO and CCRn.DIO bits are set. The CCRn.Str bit is set when the NC or AbC bit in the CSRn is set. TMP1962-194 2006-02-21 TMP1962C10BXBG * * * * * The BCRn contains a value that is not an integer multiple of the transfer size programmed into the CCRn.TrSiz field. The SARn or DARn contains a value that is not an integer multiple of the transfer size programmed into the CCRn.TrSiz field. The CCRn.TrSiz and CCRn.DPS fields contain illegal combinations. The CCRn.Str bit is set when the BCRn contains a value of zero. Bus errors When a DMA channel has terminated from a bus error, the AbC bit and the BES or BED bit in the CSRn are set. * A bus error has been reported during a source read or destination write cycle. Note: The contents of the BCRn, SARn and DARn are not guaranteed when a channel has terminated due to a bus error. Chapter 20 lists the reserved addresses that, if accessed, cause a bus error. 10.4.5 DMA Channel Priority The DMAC provides a fixed priority for the eight channels, with channel 0 always having the highest priority and channel 7 the lowest. For example, when transfer requests occur on channels 0 and 1 simultaneously, the channel 0 request is serviced first. The channel 1 request is left pending. So that the channel 1 request is serviced, it must be maintained until data transfer completes on channel 0. Remember that the internally generated request is kept until the servicing of the request is finished. External transfer requests come from the Interrupt Controller (INTC). The INTC can program any interrupts to be used as a DMA trigger instead of as an interrupt request. If such an interrupt is programmed for edge sensitivity, the INTC internally maintains a transfer request. However, a level-sensitive interrupt is not held in the INTC; thus the interrupt request signal must remain asserted until the servicing of the DMA request begins. A higher-priority channel always gets the attention of the DMAC. If a transfer request occurs on channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is suspended temporarily in order to service the channel 0 request first. After the channel 0 request has been serviced, channel 1 resumes the remaining data transfer. Channel transitions take place at the boundary of a transfer size programmed for the current channel being serviced; that is, after all data in the DHR are written to a destination. Interrupts The DMAC can generate an interrupt request (INTDMAn) to the TX19 core processor upon the completion of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle. * Normal completion interrupt When a channel operation terminates by normal completion, the NC bit in the CSRn is set to 1. At this time, if the NIEn bit in the CCRn is set, an interrupt request is generated to the TX19 core processor. * Abnormal completion interrupt When a channel operation terminates abnormally, the AbC bit in the CSRn register is set to 1. At this time, if the AbIEn bit in the CCRn register is set, an interrupt request is generated to the TX19 core processor. TMP1962-195 2006-02-21 TMP1962C10BXBG 10.5 DMA Transfer Timing All DMAC operations are synchronous to the rising edges of the internal system clock. 10.5.1 Dual-Address Mode * Memory-to-memory transfer Figure 10.16 shows a DMA cycle from one external 16-bit memory to another, with the transfer size programmed to 16 bits. A block of data is transferred until the BCRn register reaches 0. tsys A [23:0] CS0 CS1 RD WR / HWR D [15:0] Data Data Read Write Figure 10.16 Memory-to-Memory Transfer (Dual-Address Mode) * Memory-to-I/O transfer Figure 10.17 shows a DMA cycle from a 16-bit memory to an 8-bit I/O peripheral, with the transfer size programmed to 16 bits. tsys A [23:0] CS0 CS1 RD WR D [15:0] Data Data Data Read Write Write Figure 10.17 Memory-to-I/O Transfer (Dual-Address Mode) TMP1962-196 2006-02-21 TMP1962C10BXBG * I/O-to-memory transfer Figure 10.18 shows a DMA cycle from an 8-bit I/O peripheral to a 16-bit memory, with the transfer size programmed to 16 bits. tsys A [23:0] CS0 CS1 RD WR / HWR D [15:0] Data Data Data Read Read Write Figure 10.18 I/O-to-Memory Transfer (Dual-Address Mode) TMP1962-197 2006-02-21 TMP1962C10BXBG 10.5.2 Transfer Mode Responded to DREQn * Transfer from the on-chip RAM to an external memory (multiplex bus, 5 waits insertion, level mode) Figure 10.19 shows two DMA cycles from the on-chip RAM to a 16-bit external memory, with the transfer size programmed to 16 bits. (7 + ) Clock 5 Waits Internal System Clock DREQn DACKn ALE A [23:16] AD [15:0] RD Add Add Data Add Data WR HWR CSn R/ W Figure 10.19 Level Mode (Transfer from the On-chip RAM to an External Memory) * Transfer from an external memory to the on-chip RAM (multiplex bus, 5 waits insertion, level mode) Figure 10.20 shows two DMA cycles from a 16-bit external memory to the on-chip RAM, with the transfer size programmed to 16 bits. (7 + ) Clock Internal System Clock DREQn DACKn 5 Waits ALE A [23:16] AD [15:0] RD Add Add Data Add Data WR HWR CSn R/W Figure 10.20 Level Mode (Transfer from an External Memory to the On-chip RAM) TMP1962-198 2006-02-21 TMP1962C10BXBG * Transfer from the on-chip RAM to an external memory (separate bus, 5 waits insertion, level mode) Figure 10.21 shows two DMA cycles from the on-chip RAM to a 16-bit external memory, with the transfer size programmed to 16 bits. (7 + ) Clock Internal System Clock DREQn DACKn 5 Waits A [23:0] D [15:0] RD WR HWR CSn Add Data Data R/W Figure 10.21 Level Mode (Transfer from the On-chip RAM to an External Memory) * Transfer from an external memory to the on-chip RAM (separate bus, 5 waits insertion, level mode) Figure 10.22 shows two DMA cycles from a 16-bit external memory to the on-chip RAM, with the transfer size programmed to 16 bits. (7 + ) Clock 5 Waits Internal System Clock DREQn DACKn A [23:0] D [15:0] RD Add Data Data WR HWR CSn R/W Figure 10.22 Level Mode (Transfer from an External Memory to the On-chip RAM) TMP1962-199 2006-02-21 TMP1962C10BXBG * Transfer from the on-chip RAM to an external memory (multiplex bus, 5 waits insertion, edge mode) Figure 10.23 shows a DMA cycle from the on-chip RAM to a 16-bit external memory, with the transfer size programmed to 16 bits. (7 + ) Clock Internal System Clock DREQn DACKn 5 Waits ALE A [23:16] AD [15:0] RD Add Add Data WR HWR CSn R/W Figure 10.23 Edge Mode (Transfer from the On-chip RAM to an External Memory) * Transfer from an external memory to the on-chip RAM (multiplex bus, 5 waits insertion, edge mode) Figure 10.24 shows a DMA cycle from a 16-bit external memory to the on-chip RAM, with the transfer size programmed to 16 bits. (7 + ) Clock 5 Waits Internal System Clock DREQn DACKn ALE A [23:16] AD [15:0] RD WR HWR CSn Add Add Data R/W Figure 10.24 Edge Mode (Transfer from an External Memory to the On-chip RAM) TMP1962-200 2006-02-21 TMP1962C10BXBG * Transfer from the on-chip RAM to an external memory (separate bus, 5 waits insertion, edge mode) Figure 10.25 shows a DMA cycle from the on-chip RAM to a 16-bit external memory, with the transfer size programmed to 16 bits. (7 + ) Clock Internal System Clock DREQn DACKn 5 Waits A [23:0] D [15:0] RD Add Data WR HWR CSn R/W Figure 10.25 Edge Mode (Transfer from the On-chip RAM to an External Memory) * Transfer from an external memory to the on-chip RAM (separate bus, 5 waits insertion, edge mode) Figure 10.26 shows a DMA cycle from a 16-bit external memory to the on-chip RAM, with the transfer size programmed to 16 bits. (7 + ) Clock 5 Waits Internal System Clock DREQn DACKn A [23:0] D [15:0] RD WR HWR CSn Add Data R/W Figure 10.26 Edge Mode (Transfer from an External Memory to the On-chip RAM) TMP1962-201 2006-02-21 TMP1962C10BXBG 10.6 Programming Example The following illustrates the programming required to transfer data from an SIO receive buffer (SCnBUF) to the on-chip RAM. (1) DMAC settings: * * * * DMA channel used: Channel 0 Source address: SC1BUF Destination address: 0xFFFF_9800 (physical address) Number of bytes transferred: 256 (2) SIO settings: * * * Data format: 8 bits, UART SIO channel used: Channel 1 Transfer rate: 9600 bps DMA channel 0 is used for the transfer. The SIO1 receive interrupt is used as a trigger to start the DMA channel. (3) DMA channel 0 settings: DCR IMCD INTCLR DTCR0 SAR0 DAR0 BCR0 CCR0 0x8000_0000 31 23 xxxx, xxxx, xx10, x100 0x36 0x0000_0000 0xFFFF_F208 0xFFFF_9800 0x0000_00FF 0x80C0_5B0F 27 23 19 /* Reset DMAC * / /* Interrupt level = 4 (arbitrary) * / /* IVR[9:4] * / /* DACM = 000 * / /* SACM = 000 * / /* Physical address of SC1BUF */ /* Physical address of destination */ /* 256 (Number of bytes to be transferred) / (Contents) 31 1 15 0 0 0 0 11 0 0 0 1 7 1 0 0 0 3 0 0 0 0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1 (4) SIO channel 1 settings: IMC4 INTCLR SC1CR BR1CR 31 23 xxxx, xxxx, xx11, 1000 0x12 0x29 0x00 0x1F /* @fc = 40.5 MHz (approx. 1.05 Mbps) */ /* Use INTRX1 as a DMA trigger and select DMA ch. 0 * / /* IVR[9:4]; clear INTRX1 * / /* UART mode, 8-bit data format, baud rate generator * / SC1MOD0 TMP1962-202 2006-02-21 TMP1962C10BXBG 11. 8-Bit Timers (TMRAs) The TMP1962 has a twelve-channel 8-bit timer (TMRA0-TMRAB), which is comprised of six modules named TMRA01, TMRA23, TMRA45, TMRA67, TMRA89 and TMRAAB. The TMRA01 contains the TMRA0 and the TMRA1, the TMRA23 contains the TMRA2 and TMRA3, and so on. Each timer module has the following operating modes: * * * 8/16/24/32-Bit Interval Timer mode 8-Bit Programmable Pulse Generation (PPG) mode (variable frequency, variable duty cycle) 8-Bit Pulse Width Modulated (PWM) Signal Generation mode (fixed frequency, variable duty cycle) Figure 11.1 is a block diagram of the TMRA01. The main components of a timer channel are an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. Two timer channels share a prescaler and a timer flip-flop. A total of eight registers provide control over the operating modes and timer flip-flops for each timer module. The six modules are functionally equivalent and can be independently programmed. In the following sections, any references to the TMRA01 also apply to the other modules. Table 11.1 gives the pins and registers for the six timer modules. Table 11.1 Pins and Registers for TMRAs (1/3) Module Specifications External clock input External Pins Timer flip-flop output Timer Run register Timer Control register Timer registers Registers (Addresses) Timer Mode register Timer Flip-Flop Control register Timer Interrupt Mask register Timer Interrupt Status register TA0IN (Shared with PA0) TA1OUT (Shared with PA1) TA01RUN (0xFFFF_F103) TA01CR (0xFFFF_F102) TA0REG (0xFFFF_F101) TA1REG (0xFFFF_F100) TA01MOD (0xFFFF_F107) TA1FFCR (0xFFFF_F106) TAG0IM (0xFFFF_F105) TAG0ST (0xFFFF_F104) TMRA01 TA2IN TMRA23 (Shared with PA2) TA3OUT (Shared with PA3) TA23RUN (0xFFFF_F10B) TA23CR (0xFFFF_F10A) TA2REG (0xFFFF_F109) TA3REG (0xFFFF_F108) TA23MOD (0xFFFF_F10F) TA3FFCR (0xFFFF_F10E) TMP1962-203 2006-02-21 TMP1962C10BXBG Table 11.1 Pins and Registers for TMRAs (2/3) Module Specifications External clock input External Pins Timer flip-flop output Timer Run register Timer Control register Timer registers Registers (Addresses) Timer Mode register Timer Flip-Flop Control register Timer Interrupt Mask register Timer Interrupt Status register TA4IN (Shared with PL0) TA5OUT (Shared with PA4) TA45RUN (0xFFFF_F113) TA45CR (0xFFFF_F112) TA4REG (0xFFFF_F111) TA5REG (0xFFFF_F110) TA45MOD (0xFFFF_F117) TA5FFCR (0xFFFF_F116) TAG1IM (0xFFFF_F115) TAG1ST (0xFFFF_F114) TMRA45 TA6IN TMRA67 (Shared with PL1) TA7OUT (Shared with PA5) TA67RUN (0xFFFF_F11B) TA67CR (0xFFFF_F11A) TA6REG (0xFFFF_F119) TA7REG (0xFFFF_F118) TA67MOD (0xFFFF_F11F) TA7FFCR (0xFFFF_F11E) Table 11.1 Pins and Registers for TMRAs (3/3) Module Specifications External clock input External Pins Timer flip-flop output Timer Run register Timer Control register Timer registers Registers (Addresses) Timer Mode register Timer Flip-Flop Control register Timer Interrupt Mask register Timer Interrupt Status register TA8IN (Shared with PL2) TA9OUT (Shared with PA6) TA89RUN (0xFFFF_F123) TA89CR (0xFFFF_F122) TA8REG (0xFFFF_F121) TA9REG (0xFFFF_F120) TA89MOD (0xFFFF_F127) TA9FFCR (0xFFFF_F126) TAG2IM (0xFFFF_F125) TAG2ST (0xFFFF_F124) TMRA89 TAAIN TMRAAB (Shared with PL3) TABOUT (Shared with PA7) TAABRUN (0xFFFF_F12B) TAABCR (0xFFFF_F12A) TAAREG (0xFFFF_F129) TABREG (0xFFFF_F128) TAABMOD (0xFFFF_F12F) TABFFCR (0xFFFF_F12E) TMP1962-204 2006-02-21 Prescaler 8 16 32 64 128 256 512 T4 Timer Flip-Flop TA1FF TA01RUN Prescaler Clock Source: T0 2 4 T1 11.1 TMRA Block Diagram Selector External Clock Input: TA0IN T1 T4 T16 TA01MOD Figure 11.1 TMRA01 Block Diagram Match Detect TA0TRG TA01MOD Match Detect Only the TMRA01 block diagram is shown. The other timer modules are the same as the TMRA01 except the pin and register names. TMP1962-205 8-Bit Comparator (CP0) 8-Bit Comparator (CP1) 8-Bit Timer Register TA1REG Register Buffer 0 Internal Data Bus TMRA0 Match Output: TA0TRG Internal Data Bus TMRA1 Interrupt Output: INTTA1 INTTA2 INTTA3 TMRAG0 Interrupt Mask Register TAG0IM TMRAG0 Status Register TAG0ST TA01RUN TMP1962C10BXBG TMRAG0 Interrupt Output: INTTAG0 2006-02-21 TMP1962C10BXBG 11.2 Timer Components 11.2.1 Prescaler The TMRA01 has a 9-bit prescaler that slows the rate of a clocking source to the counters. The prescaler clock source (T0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The TA01PRUN bit in the TA01RUN register allows the enabling and disabling of the prescaler for the TMRA01. A write of 1 to this bit starts the prescaler. A write of 0 to this bit clears and halts the prescaler. Table 11.2 shows prescaler output clock resolutions. Table 11.2 Prescaler Output Clock Resolutions @fc = 40.5 MHz Peripheral Clock Prescaler Clock Clock Gear Source Source Value PRCK[1:0] FPSEL GEAR[1:0] 0(fgear) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 1(fc) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 5 Prescaler Output Clock Resolution T1 fc/2 (0.79 s) 5 T4 fc/2 (3.16 s) 7 6 5 8 7 6 9 8 7 T16 fc/2 (12.6 s) 9 8 7 T256 fc/2 (202 s) 13 12 fc/2 (0.4 s) 4 3 fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 7 6 5 7 6 5 7 6 5 7 6 5 fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 fc/2 (101 s) fc/2 (50.6 s) 11 fc/2 (0.2 s) fc/2 (1.58 s) 6 5 fc/2 (405 s) 14 13 12 15 14 13 fc/2 (0.79 s) fc/2 (0.4 s) 4 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (50.6 s) 11 10 9 fc/2 (202 s) fc/2 (101 s) fc/2 (809 s) fc/2 (405 s) fc/2 (202 s) fc/2 (1618 s) 16 fc/2 (3.16 s) 7 6 5 8 7 6 5 fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.4 s) 4 3 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (101 s) 12 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (50.6 s) 11 10 9 8 7 9 8 7 9 8 7 9 8 7 fc/2 (809 s) 15 14 13 12 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (405 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) 11 fc/2 (0.2 s) fc/2 (0.79 s) 5 fc/2 (202 s) 13 12 fc/2 (0.4 s) 4 3 fc/2 (101 s) fc/2 (50.6 s) 11 fc/2 (0.2 s) fc/2 (0.79 s) 5 fc/2 (202 s) 13 12 fc/2 (0.4 s) 4 fc/2 (101 s) fc/2 (50.6 s) 11 fc/2 (0.79 s) fc/2 (202 s) 13 12 fc/2 (101 s) fc/2 (50.6 s) 11 Note 1: The prescaler's output clock Tn must be selected so that Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The - character means "Setting prohibited." TMP1962-206 2006-02-21 TMP1962C10BXBG 11.2.2 Up-Counters (UC0 and UC1) The timer module contains two 8-bit binary up-counters, each of which is driven by a clock independently selected by the TA01MOD register. The clock input to the UC0 is either one of three prescaler outputs (1, T4, T16) or the external clock applied to the TA0IN pin. Which clock is to use is programmed into the TA0CLK[1:0] field of the TA01MOD register. Possible clock sources for the UC1 depend on the selected operating mode. If cascade connection is not used, the clock input to the UC1 is either one of three prescaler outputs (1, T16, T256) or the TMRA0 comparator match-detect output. If cascade connection is used to select 16-Bit Timer mode, the clock input to the UC1 is the UC0 overflow output. If cascade connection is used for 24-Bit Timer mode, the UC1 overflow output is used as the clock input to the UC2 of the TMRA23. If cascade connection is used for 32-Bit Timer mode, the UC2 overflow output is used as the clock input to the UC3. The TA0RUN and TA1RUN bits in the TA01RUN register are used to start counting and to stop and clear the counter. Upon reset, the up-counter is set to 00H and the whole timer module is disabled. 11.2.3 Timer Registers (TA0REG and TA1REG) Each timer register is an 8-bit register containing a time constant. When the up-counter reaches the time constant value in the timer register, the comparator block generates a match-detect signal. When the time constant is set to 00H, a match occurs upon a counter overflow. One of the two timer registers, TA0REG, is double-buffered. The double-buffering function can be enabled and disabled through the programming of the TA0RDE bit in the TA01RUN: 0 = disable, 1 = enable. If double-buffering is enabled, the TA0REG latches a new time constant value from the register buffer. This takes place upon detection of a 2n-1 overflow in PWM mode and upon a match between the UC0 and the TA1REG in PPG mode. Double-buffering must be disabled in interval timer modes. A reset clears the TA01RUN.TA0RDE bit to 0, disabling the double-buffering function. To use this function, the TA01RUN.TA0RDE bit must be set to 1 after loading the TA0REG with a time constant. When TA01RUN.TA0RDE = 1, the next time constant can be written to the register buffer. Figure 11.2 illustrates the double-buffer structure for the TA0REG. TMP1962-207 2006-02-21 TMP1962C10BXBG Up-Counter Comparator (CP0) Timer Register 0 (TA0REG) Y Shift Trigger Register Buffer 0 Write Selector B A TA1REG Match in PPG Mode n 2 -1 Overflow in PWM Mode Write to TA0REG S TA01RUN Figure 11.2 Timer Register 0 (TA0REG) Structure Note 1: The timer register and the corresponding register buffer are mapped to the same address. When TA01RUN.TA0RDE = 0, a time constant value is written to both the timer register and the register buffer; when TA01RUN.TA0RDE = 1, a time constant value is written only to the register buffer. Note 2: The timer registers are write-only registers. 11.2.4 Comparators (CP0 and CP1) The comparator compares the output of the 8-bit up-counter with a time constant value in the 8-bit timer register. When a match is detected, an interrupt (INTTA0/INTTA1) is generated and the timer flip-flop is toggled, if so enabled. 11.2.5 Timer Flip-Flop (TA1FF) The timer flip-flop (TA1FF) is toggled, if so enabled, each time the comparator match-detect output is asserted. The toggling of the timer flip-flop can be enabled and disabled through the programming of the TAFF1IE bit in the TA1FFCR. A reset clears the TAFF1IE bit, disabling the toggling of the TA1FF. The TA1FF can be initialized to 1 or 0 by writing 01 or 10 to the TAFF1C[1:0] field in the TA1FFCR. Additionally, a write of 00 by software causes the TA1FF to be toggled to the opposite value. The value of the TA1FF can be driven onto the TA1OUT pin, which is multiplexed with PA1. The Port A registers (PACR and PAFC) must be programmed to configure the PA1/TA1OUT pin as TA1OUT. TMP1962-208 2006-02-21 TMP1962C10BXBG 11.2.6 Interrupt Mask Register (TAG0IM) TMRA interrupts are classified into the following three groups: Interrupt Group 0 (INTTAG0): INTTA0, INTTA1, INTTA2, INTTA3 Interrupt Group 1 (INTTAG1): INTTA4, INTTA5, INTTA6, INTTA7 Interrupt Group 2 (INTTAG2): INTTA8, INTTA9, INTTAA, INTTAB Interrupts that belong to the same group are assumed as the same interrupt source when sent to the Interrupt Controller (INTC). An interrupt mask register (TAGnIM) is provided for each interrupt group. Setting a bit in the TAGnIM masks the corresponding interrupt source so that the INTC will not generate the interrupt. Upon reset, all interrupt sources are enabled (not masked). 11.2.7 Interrupt Status Register (TAG0ST) An interrupt status register (TAGnST) is provided for each interrupt group. When an interrupt occurs, the flag bit corresponding to the interrupt source is set to 1. Reading the TAGnST register clears all bits that have been set. Any interrupt sources masked in the TAGnIM register are disabled although flags are set when corresponding interrupts occur. Note: If any of INTTA0 to INTTA3 occurs while the TAG0ST is being read, the corresponding flags are handled as follows: (If the flag is set and read simultaneously.) * * If 1 is read, the flag is cleared. If 0 is read, the flag is set after the read. TMP1962-209 2006-02-21 TMP1962C10BXBG 11.3 Register Description TMRA01 Run Register 7 TA01RUN (0xFFFF_F103) Bit Symbol Read/Write Reset Value Function 0 TA0RDE 6 TA01C1 R/W 0 5 TA01C0 0 4 3 I2TA01 0 IDLE 0: Off 1: On 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: Setting prohibited 1: Enable 10: Setting prohibited 11: First stage of cascade Timer run/stop control TA0RUN: TA1RUN: I2TA01: Runs or stops the TMRA0. Runs or stops the TMRA1. Enables or disables the operation of the TMRA0-TMRA3 in IDLE mode. TA01PRUN: Runs or stops the TMRA01 prescaler. TA01C[1:0]: Specifies how the TMRA01 is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TA01M[1:0] bits in the TMRA01 Mode register. When this field is set to 11 (first stage of cascade), the TMRA01 is combined with the TMRA23 to form a 24- or 32-bit timer. TA0RDE: Enables or disables double-buffering. Note: Bit 4 of the TA01RUN is read as undefined. TMRA01 Control Register 7 TA01CR (0xFFFF_F102) Bit Symbol Read/Write Reset Value Function TA01EN R/W 0 TMRA01 operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TA01EN: Enables or disables the operation of the TMRA01. If the TMRA01 is disabled, no clock pulses are supplied to the TMRA01 registers other than the TA01CR, so that power consumption in the system can be reduced (only the TA01CR can be read or written). To use the TMRA01, set the TA01EN bit to 1 before configuring other registers of the TMRA01. Once the TMRA01 operates, all settings in its registers are held if it is disabled. The TA01EN bit enables or disables the operation of the TMRA0-TMRA3. (Enable or disable all channels of the TMRA0-TMRA3.) Note: Bits 5 and 6 of the TA01CR are read as 0. TMP1962-210 2006-02-21 TMP1962C10BXBG TMRA0 Register 7 TA0REG (0xFFFF_F101) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA0REG are read as undefined. TMRA1 Register 7 TA1REG (0xFFFF_F100) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA1REG are read as undefined. TMRA01 Mode Register 7 TA01MOD (0xFFFF_F107) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TA01M0 5 PWM01 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 2 TA1CLK0 0 1 TA0CLK1 0 00: TA0IN input 0 TA0CLK0 0 TA01M1 TMRA1 clock source 01: T1 (prescaler) 10: T16 (prescaler) 11: T256 (prescaler) TMRA0 clock source 01: T1 (prescaler) 10: T4 (prescaler) 11: T16 (prescaler) 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TA0CLK[1:0]: Selects the TMRA0 clock source. TA1CLK[1:0]: Selects the TMRA1 clock source (when the TA01M[1:0] field is set to other than 01). When TA01M[1:0] = 01, the TMRA0 overflow output is always the TMRA1 clock source regardless of the settings in TA1CLK[1:0]. PWM0[1:0]: TA01M[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. Selects the TMRA01 operating mode. When this field is set to 00, the TMRA01 is used as two independent 8-bit timers, TMRA0 and TMRA1. TMP1962-211 2006-02-21 TMP1962C10BXBG TMRA1 Flip-Flop Control Register 7 TA1FFCR (0xFFFF_F106) Bit Symbol Read/Write Reset Value Function 1 1 00: Toggles TA1FF. (software toggle) 01: Sets TA1FF to 1. 10: Clears TA1FF to 0. 11: Don't care. This field is always read as 11. 6 5 4 3 TAFF1C1 2 TAFF1C0 R/W 1 TAFF1IE 0 TA1FF toggle enable 0: Disable 1: Enable 0 TAFF1IS 0 TA1FF toggle trigger 0: TMRA0 1: TMRA1 TAFF1IS: Specifies whether Timer Flip-Flop 1 (TA1FF) is toggled by a TMRA0 match detection signal or a TMRA1 match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TA1FFCR are read as undefined. TMRAG0 Interrupt Mask Register 7 TAG0IM (0xFFFF_F105) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 TAIM3 2 TAIM2 R/W 1 TAIM1 0 0 TAIM0 0 1: Masks 1: Masks 1: Masks 1: Masks INTTA3. INTTA2. INTTA1. INTTA0. Note: Bits 4, 5, 6 and 7 of the TAG0IM are read as undefined. TMRAG0 Status Register 7 TAG0ST (0xFFFF_F104) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 INTTA3 2 INTTA2 R 1 INTTA1 0 0 INTTA0 0 0: No 0: No 0: No 0: No interrupt interrupt interrupt interrupt generated generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated generated Note 1: Reading the TAG0ST register results in bits 0, 1, 2 and 3 being cleared. Note 2: Bits 4, 5, 6 and 7 of the TAG0ST are read as undefined. Note 3: The flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. TMP1962-212 2006-02-21 TMP1962C10BXBG TMRA23 Run Register 7 TA23RUN (0xFFFF_F10B) Bit Symbol Read/Write Reset Value Function 0 TA2RDE 6 TA23C1 R/W 0 5 TA23C0 0 4 3 I2TA23 0 IDLE 0: Off 1: On 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: 24-bit cascade 1: Enable 10: 32-bit cascade 11: Setting prohibited Timer run/stop control TA2RUN: TA3RUN: I2TA23: Runs or stops the TMRA2. Runs or stops the TMRA3. Enables or disables the operation of the TMRA0-TMRA3 in IDLE mode. TA23PRUN: Runs or stops the TMRA23 prescaler. TA23C[1:0]: Specifies how the TMRA23 is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TA23M[1:0] bits in the TMRA23 Mode register. When this field is set to 01 (24-bit cascade), the TMRA2 is cascaded with the TMRA01. When this field is set to 10 (32-bit cascade), the TMRA0 to TMRA3 are cascaded. TA2RDE: Enables or disables double-buffering. Note: Bit 4 of the TA23RUN is read as undefined. TMRA23 Control Register 7 TA23CR (0xFFFF_F10A) Bit Symbol Read/Write Reset Value Function TA23EN R/W 0 TMRA23 operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TA23EN: Enables or disables the operation of the TMRA23. If the TMRA23 is disabled, no clock pulses are supplied to the TMRA23 registers other than the TA23CR, so that power consumption in the system can be reduced (only the TA23CR can be read or written). To use the TMRA23, set the TA23EN bit to 1 before configuring other registers of the TMRA23. Once the TMRA23 operates, all settings in its registers are held if it is disabled. Note: Bits 5 and 6 of the TA23CR are read as 0. TMP1962-213 2006-02-21 TMP1962C10BXBG TMRA2 Register 7 TA2REG (0xFFFF_F109) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA2REG are read as undefined. TMRA3 Register 7 TA3REG (0xFFFF_F108) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA3REG are read as undefined. TMRA23 Mode Register 7 TA23MOD (0xFFFF_F10F) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TA23M0 5 PWM21 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 2 TA3CLK0 0 1 TA2CLK1 0 00: TA2IN input 0 TA2CLK0 0 TA23M1 TMRA3 clock source 01: T1 (prescaler) 10: T16 (prescaler) 11: T256 (prescaler) TMRA2 clock source 01: T1 (prescaler) 10: T4 (prescaler) 11: T16 (prescaler) 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TA2CLK[1:0]: Selects the TMRA2 clock source. TA3CLK[1:0]: Selects the TMRA3 clock source (when the TA23M[1:0] field is set to other than 01). When TA23M[1:0] = 01, the TMRA2 overflow output is always the TMRA3 clock source regardless of the settings in TA3CLK[1:0]. PWM2[1:0]: TA23M[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. Selects the TMRA23 operating mode. When this field is set to 00, the TMRA23 is used as two independent 8-bit timers, TMRA2 and TMRA3. TMP1962-214 2006-02-21 TMP1962C10BXBG TMRA3 Flip-Flop Control Register 7 TA3FFCR (0xFFFF_F10E) Bit Symbol Read/Write Reset Value Function 1 1 00: Toggles TA3FF. (software toggle) 01: Sets TA3FF to 1. 10: Clears TA3FF to 0. 11: Don't care. This field is always read as 11. 6 5 4 3 TAFF3C1 2 TAFF3C0 R/W 1 TAFF3IE 0 TA3FF toggle enable 0: Disable 1: Enable 0 TAFF3IS 0 TA3FF toggle trigger 0: TMRA2 1: TMRA3 TAFF3IS: Specifies whether Timer Flip-Flop 3 (TA3FF) is toggled by a TMRA2 match detection signal or a TMRA3 match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TA3FFCR are read as undefined. TMRA45 Run Register 7 TA45RUN (0xFFFF_F113) Bit Symbol Read/Write Reset Value Function 0 TA4RDE 6 TA45C1 R/W 0 5 TA45C0 0 4 3 I2TA45 0 IDLE 0: Off 1: On 2 TA45PRUN 1 TA5RUN 0 R/W 0 TA4RUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: Setting prohibited 1: Enable 10: Setting prohibited 11: First stage of cascade Timer run/stop control TA4RUN: TA5RUN: I2TA45: Runs or stops the TMRA4. Runs or stops the TMRA5. Enables or disables the operation of the TMRA4-TMRA7 in IDLE mode. TA45PRUN: Runs or stops the TMRA45 prescaler. TA45C[1:0]: Specifies how the TMRA45 is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TA45M[1:0] bits in the TMRA45 Mode register. When this field is set to 11 (first stage of cascade), the TMRA45 is combined with the TMRA67 to form a 24- or 32-bit timer. TA4RDE: Enables or disables double-buffering. Note: Bit 4 of the TA45RUN is read as undefined. TMP1962-215 2006-02-21 TMP1962C10BXBG TMRA45 Control Register 7 TA45CR (0xFFFF_F112) Bit Symbol Read/Write Reset Value Function TA45EN R/W 0 TMRA45 operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TA45EN: Enables or disables the operation of the TMRA45. If the TMRA45 is disabled, no clock pulses are supplied to the TMRA45 registers other than the TA45CR, so that power consumption in the system can be reduced (only the TA45CR can be read or written). To use the TMRA45, set the TA45EN bit to 1 before configuring other registers of the TMRA45. Once the TMRA45 operates, all settings in its registers are held if it is disabled. The TA45EN bit enables or disables the operation of the TMRA4-TMRA7. (Enable or disable all channels of the TMRA4-TMRA7.) Note: Bits 5 and 6 of the TA45CR are read as 0. TMRA4 Register 7 TA4REG (0xFFFF_F111) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA4REG are read as undefined. TMRA5 Register 7 TA5REG (0xFFFF_F110) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA5REG are read as undefined. TMP1962-216 2006-02-21 TMP1962C10BXBG TMRA45 Mode Register 7 TA45MOD (0xFFFF_F117) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TA45M0 5 PWM41 4 PWM40 0 R/W 3 TA5CLK1 0 00: TA4TRG 01: T1 10: T16 11: T256 2 TA5CLK0 0 1 TA4CLK1 0 00: TA4IN input 01: T1 10: T4 11: T16 0 TA4CLK0 0 TA45M1 TMRA5 clock source TMRA4 clock source 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TA4CLK[1:0]: Selects the TMRA4 clock source. TA5CLK[1:0]: Selects the TMRA5 clock source (when the TA45M[1:0] field is set to other than 01). When TA45M[1:0] = 01, the TMRA4 overflow output is always the TMRA5 clock source regardless of the settings in TA5CLK[1:0]. PWM4[1:0]: TA45M[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. Selects the TMRA45 operating mode. When this field is set to 00, the TMRA45 is used as two independent 8-bit timers, TMRA4 and TMRA5. TMRA5 Flip-Flop Control Register 7 TA5FFCR (0xFFFF_F116) Bit Symbol Read/Write Reset Value Function 1 (software toggle) 01: Sets TA5FF to 1. 10: Clears TA5FF to 0. 11: Don't care. This field is always read as 11. 1 00: Toggles TA5FF. 6 5 4 3 TAFF5C1 2 TAFF5C0 R/W 1 TAFF5IE 0 TA5FF toggle enable 0: Disable 1: Enable 0 TAFF5IS 0 TA5FF toggle trigger 0: TMRA4 1: TMRA5 TAFF5IS: Specifies whether Timer Flip-Flop 5 (TA5FF) is toggled by a TMRA4 match detection signal or a TMRA5 match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TA5FFCR are read as undefined. TMRAG1 Interrupt Mask Register 7 TAG1IM (0xFFFF_F115) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 TAIM7 2 TAIM6 R/W 1 TAIM5 0 0 TAIM4 0 1: Masks 1: Masks 1: Masks 1: Masks INTTA7. INTTA6. INTTA5. INTTA4. Note: Bits 4, 5, 6 and 7 of the TAG1IM are read as undefined. TMP1962-217 2006-02-21 TMP1962C10BXBG TMRAG1 Status Register 7 TAG1ST (0xFFFF_F114) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 INTTA7 2 INTTA6 R 1 INTTA5 0 0 INTTA4 0 0: No 0: No 0: No 0: No interrupt interrupt interrupt interrupt generated generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated generated Note 1: Reading the TAG1ST register results in bits 0, 1, 2 and 3 being cleared. Note 2: Bits 4, 5, 6 and 7 of the TAG1ST are read as undefined. Note 3: The flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. TMRA67 Run Register 7 TA67RUN (0xFFFF_F11B) Bit Symbol Read/Write Reset Value Function 0 TA6RDE 6 TA67C1 R/W 0 5 TA67C0 0 4 3 I2TA67 0 IDLE 0: Off 1: On 2 TA67PRUN 1 TA7RUN 0 R/W 0 TA6RUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: 24-bit cascade 1: Enable 10: 32-bit cascade 11: Setting prohibited Timer run/stop control TA6RUN: TA7RUN: TA67PRUN: I2TA67: TA67C[1:0]: Runs or stops the TMRA6. Runs or stops the TMRA7. Runs or stops the TMRA67 prescaler. Enables or disables the operation of the TMRA4-TMRA7 in IDLE mode. Specifies how the TMRA67 is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TA67M[1:0] bits in the TMRA67 Mode register. When this field is set to 01 (24-bit cascade), the TMRA6 is cascaded with the TMRA45. When this field is set to 10 (32-bit cascade), the TMRA4 to TMRA7 are cascaded. Enables or disables double-buffering. TA6RDE: Note: Bit 4 of the TA67RUN is read as undefined. TMP1962-218 2006-02-21 TMP1962C10BXBG TMRA67 Control Register 7 TA67CR (0xFFFF_F11A) Bit Symbol Read/Write Reset Value Function TA67EN R/W 0 TMRA67 operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TA67EN: Enables or disables the operation of the TMRA67. If the TMRA67 is disabled, no clock pulses are supplied to the TMRA67 registers other than the TA67CR, so that power consumption in the system can be reduced (only the TA67CR can be read or written). To use the TMRA67, set the TA67EN bit to 1 before configuring other registers of the TMRA67. Once the TMRA67 operates, all settings in its registers are held if it is disabled. Note: Bits 5 and 6 of the TA67CR are read as 0. TMRA6 Register 7 TA6REG (0xFFFF_F119) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA6REG are read as undefined. TMRA7 Register 7 TA7REG (0xFFFF_F118) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA7REG are read as undefined. TMP1962-219 2006-02-21 TMP1962C10BXBG TMRA67 Mode Register 7 TA67MOD (0xFFFF_F11F) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TA67M0 5 PWM61 4 PWM60 0 R/W 3 TA7CLK1 0 00: TA6TRG 01: T1 10: T16 11: T256 2 TA7CLK0 0 1 TA6CLK1 0 00: TA6IN input 01: T1 10: T4 11: T16 0 TA6CLK0 0 TA67M1 TMRA7 clock source TMRA6 clock source 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TA6CLK[1:0]: Selects the TMRA6 clock source. TA7CLK[1:0]: Selects the TMRA7 clock source (when the TA67M[1:0] field is set to other than 01). When TA67M[1:0] = 01, the TMRA6 overflow output is always the TMRA7 clock source regardless of the settings in TA7CLK[1:0]. PWM6[1:0]: TA67M[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. Selects the TMRA67 operating mode. When this field is set to 00, the TMRA67 is used as two independent 8-bit timers, TMRA6 and TMRA7. TMRA7 Flip-Flop Control Register 7 TA7FFCR (0xFFFF_F11E) Bit Symbol Read/Write Reset Value Function 1 1 00: Toggles TA7FF. (software toggle) 01: Sets TA7FF to 1. 10: Clears TA7FF to 0. 11: Don't care. This field is always read as 11. 6 5 4 3 TAFF7C1 2 TAFF7C0 R/W 1 TAFF7IE 0 TA7FF toggle enable 0: Disable 1: Enable 0 TAFF7IS 0 TA7FF toggle trigger 0: TMRA6 1: TMRA7 TAFF7IS: Specifies whether Timer Flip-Flop 7 (TA7FF) is toggled by a TMRA6 match detection signal or a TMRA7 match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TA7FFCR are read as undefined. TMP1962-220 2006-02-21 TMP1962C10BXBG TMRA89 Run Register 7 TA89RUN (0xFFFF_F123) Bit Symbol Read/Write Reset Value Function 0 TA8RDE 6 TA89C1 R/W 0 5 TA89C0 0 4 3 I2TA89 0 IDLE 0: Off 1: On 2 TA89PRUN 1 TA9RUN 0 R/W 0 TA8RUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: Setting prohibited 1: Enable 10: Setting prohibited 11: First stage of cascade Timer run/stop control TA8RUN: TA9RUN: TA89PRUN: I2TA89: TA89C[1:0]: Runs or stops the TMRA8. Runs or stops the TMRA9. Runs or stops the TMRA89 prescaler. Enables or disables the operation of the TMRA8-TMRAB in IDLE mode. Specifies how the TMRA89 is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TA89M[1:0] bits in the TMRA89 Mode register. When this field is set to 11 (first stage of cascade), the TMRA89 is combined with the TMRAAB to form a 24- or 32-bit timer. Enables or disables double-buffering. TA8RDE: Note: Bit 4 of the TA89RUN is read as undefined. TMRA89 Control Register 7 TA89CR (0xFFFF_F122) Bit Symbol Read/Write Reset Value Function TA89EN R/W 0 TMRA89 operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TA89EN: Enables or disables the operation of the TMRA89. If the TMRA89 is disabled, no clock pulses are supplied to the TMRA89 registers other than the TA89CR, so that power consumption in the system can be reduced (only the TA89CR can be read or written). To use the TMRA89, set the TA89EN bit to 1 before configuring other registers of the TMRA89. Once the TMRA89 operates, all settings in its registers are held if it is disabled. The TA89EN bit enables or disables the operation of the TMRA8-TMRAB. (Enable or disable all channels of the TMRA8-TMRAB.) Note: Bits 5 and 6 of the TA89CR are read as 0. TMP1962-221 2006-02-21 TMP1962C10BXBG TMRA8 Register 7 TA8REG (0xFFFF_F121) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TA8REG are read as undefined. TMRA9 Register 7 TA9REG (0xFFFF_F120) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Note: Bits 7-0 of the TA9REG are read as undefined. TMRA89 Mode Register 7 TA89MOD (0xFFFF_F127) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TA89M0 5 PWM81 4 PWM80 0 R/W 3 TA9CLK1 0 00: TA8TRG 01: T1 10: T16 11: T256 2 TA9CLK0 0 1 TA8CLK1 0 00: TA8IN input 01: T1 10: T4 11: T16 0 TA8CLK0 0 TA89M1 TMRA9 clock source TMRA8 clock source 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TA8CLK[1:0]: Selects the TMRA8 clock source. TA9CLK[1:0]: Selects the TMRA9 clock source (when the TA89M[1:0] field is set to other than 01). When TA89M[1:0] = 01, the TMRA8 overflow output is always the TMRA9 clock source regardless of the settings in TA9CLK[1:0]. PWM8[1:0]: TA89M[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. Selects the TMRA89 operating mode. When this field is set to 00, the TMRA89 is used as two independent 8-bit timers, TMRA8 and TMRA9. TMP1962-222 2006-02-21 TMP1962C10BXBG TMRA9 Flip-Flop Control Register 7 TA9FFCR (0xFFFF_F126) Bit Symbol Read/Write Reset Value Function 1 1 00: Toggles TA9FF. (software toggle) 01: Sets TA9FF to 1. 10: Clears TA9FF to 0. 11: Don't care. This field is always read as 11. 6 5 4 3 TAFF9C1 2 TAFF9C0 R/W 1 TAFF9IE 0 TA9FF toggle enable 0: Disable 1: Enable 0 TAFF9IS 0 TA9FF toggle trigger 0: TMRA8 1: TMRA9 TAFF9IS: Specifies whether Timer Flip-Flop 9 (TA9FF) is toggled by a TMRA8 match detection signal or a TMRA9 match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TA9FFCR are read as undefined. TMRAG2 Interrupt Mask Register 7 TAG2IM (0xFFFF_F125) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 TAIMB 2 TAIMA R/W 1 TAIM9 0 0 TAIM8 0 1: Masks 1: Masks 1: Masks 1: Masks INTTAB. INTTAA. INTTA9. INTTA8. Note: Bits 4, 5, 6 and 7 of the TAG2IM are read as undefined. TMRAG2 Status Register 7 TAG2ST (0xFFFF_F124) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 INTTAB 2 INTTAA R 1 INTTA9 0 0 INTTA8 0 0: No 0: No 0: No 0: No interrupt interrupt interrupt interrupt generated generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated generated Note 1: Reading the TAG2ST register results in bits 0, 1, 2 and 3 being cleared. Note 2: Bits 4, 5, 6 and 7 of the TAG2ST are read as undefined. Note 3: The flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. TMP1962-223 2006-02-21 TMP1962C10BXBG TMRAAB Run Register 7 TAABRUN (0xFFFF_F12B) Bit Symbol Read/Write Reset Value Function 0 TAARDE 6 TAABC1 R/W 0 5 TAABC0 0 4 3 I2TAAB 0 IDLE 0: Off 1: On 2 TAABPRUN 1 TABRUN 0 R/W 0 TAARUN 0 0 0: Stop & clear 1: Run Double-bu Cascade connection ffering 00: 8- or 16-bit mode 0: Disable 01: 24-bit cascade 1: Enable 10: 32-bit cascade 11: Setting prohibited Timer run/stop control TAARUN: TABRUN: I2TAAB: TAABC[1:0]: Runs or stops the TMRAA. Runs or stops the TMRAB. Enables or disables the operation of the TMRA8-TMRAB in IDLE mode. Specifies how the TMRAAB is used in cascade connection. When this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the TAABM[1:0] bits in the TMRAAB Mode register. When this field is set to 01 (24-bit cascade), the TMRAA is cascaded with the TMRA89. When this field is set to 10 (32-bit cascade), the TMRA8 to TMRAB are cascaded. Enables or disables double-buffering. TAABPRUN: Runs or stops the TMRAAB prescaler. TAARDE: Note: Bit 4 of the TAABRUN is read as undefined. TMRAAB Control Register 7 TAABCR (0xFFFF_F12A) Bit Symbol Read/Write Reset Value Function TAABEN R/W 0 TMRAAB operation 0: Disable 1: Enable 0 0 Must be written as 00. 6 5 4 3 2 1 0 TAABEN: Enables or disables the operation of the TMRAAB. If the TMRAAB is disabled, no clock pulses are supplied to the TMRAAB registers other than the TAABCR, so that power consumption in the system can be reduced (only the TAABCR can be read or written). To use the TMRAAB, set the TAABEN bit to 1 before configuring other registers of the TMRAAB. Once the TMRAAB operates, all settings in its registers are held if it is disabled. Note: Bits 5 and 6 of the TAABCR are read as 0. TMP1962-224 2006-02-21 TMP1962C10BXBG TMRAA Register 7 TAAREG (0xFFFF_F129) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TAAREG are read as undefined. TMRAB Register 7 TABREG (0xFFFF_F128) Bit Symbol Read/Write Function W Timer register 6 5 4 3 2 1 0 Note: Bits 7-0 of the TABREG are read as undefined. TMRAAB Mode Register 7 TAABMOD (0xFFFF_F12F) Bit Symbol Read/Write Reset Value Function 0 Operating mode 00: 8-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM period 00: Reserved 6 7 8 6 TAABM0 5 PWMA1 4 PWMA0 0 R/W 3 TABCLK1 0 00: TAATRG 01: T1 10: T16 11: T256 2 TABCLK0 0 1 TAACLK1 0 00: TAAIN input 01: T1 10: T4 11: T16 0 TAACLK0 0 TAABM1 TMRAB clock source TMRAA clock source 01: 16-bit interval timer 01: 2 - 1 10: 2 - 1 11: 2 - 1 TAACLK[1:0]: Selects the TMRAA clock source. TABCLK[1:0]: Selects the TMRAB clock source (when the TAABM[1:0] field is set to other than 01). When TAABM[1:0] = 01, the TMRAA overflow output is always the TMRAB clock source regardless of the settings in TABCLK[1:0]. PWMA[1:0]: Selects the period for 8-bit PWM mode. The PWM period will be (2n - 1) x clock source period. TAABM[1:0]: Selects the TMRAAB operating mode. When this field is set to 00, the TMRAAB is used as two independent 8-bit timers, TMRAA and TMRAB. TMP1962-225 2006-02-21 TMP1962C10BXBG TMRAB Flip-Flop Control Register 7 TABFFCR (0xFFFF_F12E) Bit Symbol Read/Write Reset Value Function 1 (software toggle) 01: Sets TABFF to 1. 10: Clears TABFF to 0. 11: Don't care. This field is always read as 11. 1 00: Toggles TABFF. 6 5 4 3 TAFFBC1 2 TAFFBC0 R/W 1 TAFFBIE 0 TABFF toggle enable 0: Disable 1: Enable 0 TAFFBIS 0 TA3FF toggle trigger 0: TMRAA 1: TMRAB TAFFBIS: Specifies whether Timer Flip-Flop B (TABFF) is toggled by a TMRAA match detection signal or a TMRAB match detection signal. This bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. Note: Bits 4, 5, 6 and 7 of the TABFFCR are read as undefined. TMP1962-226 2006-02-21 TMP1962C10BXBG 11.4 Operating Modes 11.4.1 8-Bit Interval Timer Mode The TMRA0 and the TMRA1 can be independently programmed as 8-bit interval timers. Programming these timers should only be attempted when the timers are not running. (1) Generating periodic interrupts In the following example, the TMRA1 is used to accomplish periodic interrupt generation. First, stop the TMRA1 (if it is running). Then, set the operating mode, clock source and interrupt interval in the TA01MOD and TA1REG registers. Then, enable the INTTA1 interrupt and start the TMRA1. Example: Generating the INTTA1 interrupt at a 20-s interval (fc = 40.5 MHz) Clocking conditions: System clock: Prescaler clock: MSB 7 TA01RUN TA01MOD TA1REG IMC6LH TA01RUN - 0 0 X - 6 0 0 1 X - 5 0 X 1 1 - 4 X X 0 1 X 3 - 1 0 0 - 2 - 0 1 1 1 LSB 1 0 X 0 0 1 0 - X 0 1 - Stops and clears the TMRA1. Selects 8-Bit Interval Timer mode and T1 as the clock source (which provides a 0.2-s resolution @fc = 40.5 MHz). Sets the time constant value in the TA1REG (20 s / T1 = 100 (64H)). Enables INTTAGA0 and sets the interrupt level to 5. INTTA1 must always be programmed to be rising-edge triggered. Starts the TMRA1. High-speed (fc) fperiph/4 (fperiph = fsys) X = Don't care, - = No change Refer to Table 11.2 when selecting a timer clock source. Note: The clock inputs to the TMRA0 and the TMRA1 can be one of the following: TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match-detect signal from the TMRA0, T1, T16 or T256 TMP1962-227 2006-02-21 TMP1962C10BXBG (2) Generating a square wave with a 50% duty cycle The 8-Bit Interval Timer mode can be used to generate square-wave output. This is accomplished by toggling the timer flip-flop (TA1FF) periodically. The TA1FF state can be driven out to the TA1OUT pin. Both the TMRA0 and the TMRA1 can be used as square-wave generators. The following shows an example using the TMRA1. Example: Generating square-wave output with a 1.2-s period on the TA1OUT pin (fc = 40.5 MHz) Clocking conditions: System clock: High-speed clock gear: Prescaler clock: 7 TA01RUN TA01MOD TA1REG TA1FFCR PACR PAFC TA01RUN - 0 0 X - - - 6 0 0 0 X - - - 5 0 X 0 X - - - 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 - - 1 1 0 - 1 1 1 1 1 0 - - 1 1 - - - Stops and clears the TMRA1. Selects 8-Bit Interval Timer mode and T1 as the clock source (which provides a 0.2-s resolution @fc = 40.5 MHz). Sets the time constant value in the TA1REG (1.2 s / T1 / 2 = 3). Clears the TA1FF to 0 and selects the TMRA1 match-detect output as a toggle-trigger signal. Configures PA1 as the TA1OUT output pin. Starts the TMRA1. High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) X = Don't care, - = No change T1 TA01RUN 0 1 2 3 0 1 2 3 0 1 2 3 0 Up-Counter Clear TA1FF TA1OUT 0.6s @fc = 40.5 MHz Figure 11.3 Square-Wave Generation (50% Duty Cycle) TMP1962-228 2006-02-21 TMP1962C10BXBG (3) Using the TMRA0 match-detect output as a trigger for the TMRA1 Set the TMRA01 in 8-Bit Interval Timer mode. Select the TMRA0 comparator match-detect output as the clock source for the TMRA1. TMRA0 Comparator Match Output TMRA0 Up-Counter (when TA0REG = 5) TMRA1 Up-Counter (when TA1REG = 2) TMRA1 Match Output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 11.4 Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1 11.4.2 16/24/32-Bit Interval Timer Mode (1) 16-Bit Interval Timer mode The TMRA0 and the TMRA1 are cascadable to form a 16-bit interval timer. The TMRA01 is put in 16-Bit Interval Timer mode by programming the TA01M[1:0] field in the TA01MOD register to 01. In 16-Bit Interval Timer mode, the TMRA1 is clocked by the counter overflow output from the TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are Don't-cares. The clock input to the TMRA0 can be selected as shown in Table 11.4. Write the lower eight bits of a time constant value to the TA0REG and the upper eight bits to the TA1REG. Programming these registers should only be attempted when the timers are not running. Example: Generating the INTTA1 interrupt at a 0.1-second interval (fc = 40.5 MHz) Clocking conditions: System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) Under the above conditions, T16 has a period of 3.16 s @ 40.5 MHz. When T16 is used as the TMRA0 clock source, the required time constant value is calculated as follows: 0.1 s / 3.16 s = 31646 = 7B9EH Thus, the TA1REG is to be set to 7BH and the TA0REG to 9EH. TMP1962-229 2006-02-21 TMP1962C10BXBG Every time the up-counter UC0 reaches the value in the TA0REG, the TMRA0 comparator generates a match-detect output, but the UC0 continues counting up. A match between the UC0 and the TA0REG does not cause an INTTA0 interrupt. Every time the up-counter UC1 reaches the value in the TA1REG, the TMRA1 comparator generates a match-detect output. When the TMRA0 and TMRA1 match-detect outputs are asserted simultaneously, both the up-counters (UC0 and UC1) are reset to 00H and an interrupt is generated on INTTA1. Also, if so enabled, the timer flip-flop (TA1FF) is toggled. Example: TA1REG = 04H and TA0REG = 80H Up-Counter Values 0000H (UC1/UC0) Match-Detect Signal from the TMRA0 Comparator INTTA1 Interrupt TA1OUT Timer Output Toggled 0080H 0180H 0280H 0380H 0480H Figure 11.5 Timer Output in 16-Bit Interval Timer Mode (2) 24-Bit Interval Timer mode The pair of the TMRA0 and TMRA1 can further be cascaded with the TMRA2 to form a 24-bit interval timer. In 24-Bit Interval Timer mode, the TMRA1 is clocked by the counter overflow output from the TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are Don't-cares. The TMRA2 is clocked by the counter overflow output from the TMRA1. The clock input to the TMRA0 can be selected as shown in Table 11.4. Write the lowest eight bits of a time constant value to the TA0REG, the middle eight bits to the TA1REG and the highest eight bits to the TA2REG. Programming these registers should only be attempted when the timers are not running. (3) 32-Bit Interval Timer mode The TMRA0, TMRA1, TMRA2 and TMRA3 are put in 32-Bit Interval Timer mode by programming the TA01M[1:0] field in the TA01MOD register to 01 and the TA32M0 bit in the TA32MOD register to 1. In 32-Bit Interval Timer mode, the TMRA1 is clocked by the counter overflow output from the TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are Don't-cares. Likewise, the TMRA3 is clocked by the counter overflow output from the TMRA2 and the TA3CLK[1:0] bits in the TA23MOD register are Don't-cares. The TMRA2 is clocked by the counter overflow output from the TMRA1. The clock input to the TMRA0 can be selected as shown in Table 11.4. Write the lowest eight bits of a time constant value to the TA0REG, the next eight bits to the TA1REG, the next eight bits to the TA2REG and the highest eight bits to the TA3REG. Programming these registers should only be attempted when the timers are not running. TMP1962-230 2006-02-21 TMP1962C10BXBG (4) Cascade combinations In 16-Bit Interval Timer mode: Upper TMRA3 TMRA7 TMRAB Lower TMRA2 TMRA6 TMRAA Upper TMRA1 TMRA5 TMRA9 Lower TMRA0 TMRA4 TMRA8 In 24-Bit Interval Timer mode: Highest TMRA2 TMRA6 TMRAA TMRA1 TMRA5 TMRA9 Lowest TMRA0 TMRA4 TMRA8 Note: In 24-Bit Interval Timer mode, the TMRA3, TMRA7 and TMRAB can operate as an independent 8-bit timer. In 32-Bit Interval Timer mode: Highest TMRA3 TMRA7 TMRAB TMRA2 TMRA6 TMRAA TMRA1 TMRA5 TMRA9 Lowest TMRA0 TMRA4 TMRA8 11.4.3 8-Bit Programmable Pulse Generation (PPG) Mode The 8-Bit PPG mode can be used to generate a square wave with any frequency and duty cycle, as shown below. The pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (TA1FF). This mode is supported by the TMRA0, but not by the TMRA1. The square wave output is driven to the TA1OUT pin (which is multiplexed with PA1). tH tL t Match Between TA0REG and Up-Counter 0 (INTTA0) Match Between TA1REG and Up-Counter 0 (INTTA1) TA1OUT TA0REG TA1REG Figure 11.6 8-Bit PPG Output Waveform TMP1962-231 2006-02-21 TMP1962C10BXBG In this mode, a square wave is generated by toggling the timer flip-flop (TA1FF). The TA1FF changes state every time a match is detected between the UC0 and the TA0REG and between the UC0 and the TA1REG. The TA0REG must be set to a value less than the TA1REG value. In this mode, the TMRA1 up-counter (UC1) cannot be independently used; however, the TMRA1 must be put in a running state by setting the TA1RUN bit in the TA01RUN register to 1. Figure 11.7 shows a functional diagram of 8-Bit PPG mode. TA1OUT Selector T1 T4 T16 8-Bit Up-Counter (UC0) TA01RUN Toggle TA01MOD Selector TA0REG-WR TA0REG Shift-Trigger Register Buffer TA1REG TA01RUN Internal Data Bus Figure 11.7 Functional Diagram of 8-Bit PPG Mode In 8-Bit PPG mode, if the double-buffering function is enabled, the TA0REG value can be changed dynamically by writing a new value into the register buffer. Upon a match between the TA1REG and the UC0, the TA0REG latches a new value from the register buffer. The TA0REG can be loaded with a new value upon every match, thus making it easy to generate a square wave with a variable duty cycle. Match Between TA0REG and Up-Counter 0 Match Between TA1REG and Up-Counter 0 TA0REG (compare value) Register Buffer (Up-Counter = Q1) (Up-Counter = Q2) Shift-Trigger for Register Buffer Q2 Q2 Q3 Write to TA0REG (Register Buffer) Q1 Figure 11.8 Register Buffer Operation TMP1962-232 2006-02-21 TMP1962C10BXBG Example: Generating a 50-kHz square wave with a 25% duty cycle (fc = 40.5 MHz) 20 s Clocking conditions: System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) The time constant values to be loaded into the TA0REG and TA1REG are determined as follows: A 50-kHz waveform has a period of 20 s. Under the above clocking conditions, T1 has a 0.2-s resolution (@fc = 40.5 MHz). When T1 is used as the timer clock source, the TA1REG should be loaded with: 20 s / 0.2 s = 100 (64H) With a 25% duty cycle, the high pulse width is calculated as 20 s x 1/4 = 5 s. Thus, the TA0REG should be loaded with: 5 s / 0.2 s = 25 (19H) 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 0 1 0 0 X 6 0 0 0 1 X 5 0 X 0 1 X 4 X X 1 0 X 3 - X 1 0 0 2 0 X 0 1 1 1 0 0 0 0 1 0 0 1 1 0 X Stops and clears the TMRA0 and the TMRA1. Selects 8-Bit PPG mode and T1 as the clock source. Writes 19H. Writes 64H. Sets the TA1FF to 1 and enables toggling. If these bits are set to 10, a low-going pulse is generated. PACR PAFC TA01RUN - - 1 - - - - - - - - X - - - - - 1 1 1 1 - - 1 Configures PA1 as the TA1OUT output pin. Starts the TMRA0 and the TMRA1. X = Don't care, - = No change TMP1962-233 2006-02-21 TMP1962C10BXBG 11.4.4 8-Bit PWM Generation Mode The TMRA0 can be used as a pulse-width modulated (PWM) signal generator with up to 8 bits of resolution. This mode is supported by the TMRA0, but not by the TMRA1. The PWM signal is driven out on the TA1OUT pin (which is multiplexed with P71). While the TMRA01 is in this mode, the TMRA1 is usable as an 8-bit interval timer. The timer flip-flop toggles when the up-counter (UC0) reaches the TA0REG value and when a 2n-1 counter overflow occurs, where n is programmable to 6, 7 or 8 through the PWM[01:00] field in the TA01MOD register. The UC0 is reset to 00H upon a 2n-1 overflow. In 8-Bit PWM Generation mode, the following must be satisfied: (TA0REG value) < (2n-1 counter overflow value) (TA0REG value) 0 Match Between TA0REG and Up-Counter 0 2 -1 Overflow (INTTA0 Interrupt) n TA1OUT tPWM (PWM Cycle) Figure 11.9 8-Bit PWM Signal Generation Figure 11.10 shows a functional diagram of 8-Bit PWM Generation mode. TA01RUN n T4 T16 T1 Selector 8-Bit Up-Counter (UC0) Clear TA1FFCR TA01MOD Figure 11.10 Functional Diagram of 8-Bit PWM Generation Mode TMP1962-234 2006-02-21 TMP1962C10BXBG In 8-Bit PWM Generation mode, if the double-buffering function is enabled, the TA0REG value (i.e., the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2n-1 counter overflow, the TA0REG latches a new value from the register buffer. The TA0REG can be loaded with a new value upon every counter overflow, thus making it easy to generate a PWM signal with a variable duty cycle. Match Between TA0REG and Up-Counter 0 2 -1 Overflow TA0REG (compare value) Register Buffer Q1 Q2 Shift into TA0REG Q2 Q3 Write to TA0REG (Register Buffer) n Up-Counter = Q1 Up-Counter = Q2 Figure 11.11 Register Buffer Operation Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 40.5 MHz) 20 s 25 s Clocking conditions: System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) Under the above conditions, T1 has a 0.2-s (0.197-s) period (@fc = 40.5 MHz). 25 s / 0.197 s = 127 which is equal to 27 - 1. 20 s / 0.2 s = 100 = 64H Hence, the time constant value to be programmed into the TA0REG is 64H. MSB 7 TA01RUN TA01MOD - 1 6 0 1 5 0 1 4 X 0 3 - - 2 - - LSB 1 - 0 0 0 1 Stops and clears the TMRA0. Selects 8-Bit PWM mode (period = 2 -1) and T1 as the clock source. 7 TA0REG TA1FFCR PACR PAFC TA01RUN 0 X - - 1 1 X - - - 1 X - - - 0 X - - X 0 1 - - - 1 0 - - 1 0 1 1 1 - 0 X - - 1 Writes 64H. Clears the TA1FF to 0 and enables toggling. Configures PA1 as the TA1OUT output pin. Starts the TMRA0. X = Don't care, - = No change TMP1962-235 2006-02-21 TMP1962C10BXBG Table 11.3 PWM Period @fc = 40.5 MHz Peripheral Clock Gear Clock Select Value FPSEL GEAR[1:0] 0(fgear) 00(fc) Prescaler Clock Source PRCK[1:0] 01(fperiph/8) 10(fperiph/4) PWM Period 2 -1 T1 T4 199 s 6 27-1 T16 796 s 398 s 199 s 796 s 398 s 28-1 T16 803 s 401 s T1 100 s 50.2 s 25.1 s 201 s 100 s 50.2 s 201 s 100 s T4 201 s 100 s T1 201 s 101 s 50.3 s 201 s 101 s T4 T16 00(fperiph/16) 49.8 s 401 s 1.61 ms 806 s 3.22 ms 403 s 1.61 ms 201 s 806 s 24.9 s 99.6 s 12.4 s 49.8 s 49.8 s 199 s 99.6 s 49.8 s 199 s 99.6 s 199 s 01(fc/2) 00(fperiph/16) 99.6 s 01(fperiph/8) 10(fperiph/4) 398 s 1.59 ms 803 s 3.21 ms 401 s 1.61 ms 201 s 803 s 403 s 1.61 ms 6.45 ms 806 s 3.22 ms 403 s 1.61 ms 24.9 s 99.6 s 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 796 s 3.19 ms 398 s 1.59 ms 199 s 796 s 401 s 1.61 ms 6.42 ms 803 s 3.21 ms 401 s 1.61 ms 806 s 3.22 ms 12.9 ms 403 s 1.61 ms 6.45 ms 201 s 806 s 3.22 ms 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 398 s 1.59 ms 6.37 ms 796 s 3.19 ms 398 s 1.59 ms 199 s 796 s 398 s 199 s 796 s 398 s 199 s 796 s 398 s 199 s 796 s 398 s 199 s 803 s 3.21 ms 12.8 ms 1.61 ms 6.45 ms 25.8 ms 401 s 1.61 ms 6.42 ms 201 s 100 s 50.2 s 25.1 s 100 s 50.2 s 25.1 s 100 s 50.2 s 100 s 803 s 3.21 ms 401 s 1.61 ms 201 s 100 s 201 s 100 s 201 s 100 s 201 s 100 s 803 s 401 s 803 s 401 s 803 s 401 s 803 s 401 s 806 s 3.22 ms 12.9 ms 403 s 1.61 ms 6.45 ms 201 s 101 s 50.3 s 201 s 101 s 50.3 s 201 s 101 s 201 s 806 s 3.22 ms 403 s 1.61 ms 201 s 806 s 806 s 3.22 ms 403 s 1.61 ms 201 s 806 s 806 s 3.22 ms 403 s 1.61 ms 201 s 806 s 806 s 3.22 ms 403 s 1.61 ms 201 s 806 s 1(fc) 00(fc) 00(fperiph/16) 49.8 s 01(fperiph/8) 10(fperiph/4) 24.9 s 99.6 s 12.4 s 49.8 s 199 s 24.9 s 99.6 s 12.4 s 49.8 s 199 s 49.8 s 199 s 99.6 s 49.8 s 24.9 s 99.6 s 01(fc/2) 00(fperiph/16) 49.8 s 01(fperiph/8) 10(fperiph/4) 401 s 1.61 ms 10(fc/4) 00(fperiph/16) 49.8 s 01(fperiph/8) 10(fperiph/4) 401 s 1.61 ms 11(fc/8) 00(fperiph/16) 49.8 s 01(fperiph/8) 10(fperiph/4) 401 s 1.61 ms Note 1: The prescaler's output clock Tn must be selected so that Tn < fsys/2 is satisfied. Note 2: The - character means "Setting prohibited." TMP1962-236 2006-02-21 TMP1962C10BXBG 11.4.5 Operating Mode Summary Table 11.4 shows the settings for the TMRA01 for each of the operating modes. Table 11.4 Register Settings for Each Operating Mode Register Field Function TA01RUN TA01MOD Match output from UC0 T1, T16, T256 (00, 01, 10, 11) TA1FFCR External clock, T1, T4, T16 (00, 01, 10, 11) External clock, TAFF1IS Timer Flip-Flop Toggle Trigger 0: UC0 output 1: UC1 output 8-Bit Timer x 2ch 00 00 16-Bit Timer Mode 00 01 T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11 External clock, T1, T4, T16 (00, 01, 10, 11 External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) 24-Bit Timer Mode 11 32-Bit Timer Mode 11 8-Bit PPG x 1ch 00 10 8-Bit PWM x 1ch 8-Bit Timer (Note 2) 00 11 26 - 1, 27 - 1, 28 - 1 (01, 10, 11) T1, T16 , T256 (01, 10, 11) PWM output Note 1: - = Don't care Note 2: In 8-Bit PWM mode, the UC1 can be used as an 8-bit timer. However, the match-detect output from the UC0 cannot be used as a clock source for the UC1, and the timer output is not available for the UC1. TMP1962-237 2006-02-21 TMP1962C10BXBG 12. 16-Bit Timer/Event Counters (TMRBs) The TMP1962 has a 16-bit timer/event counter consisting of four identical channels (TMRB0-TMRB3). Each channel has the following four basic operating modes: * * * * 16-Bit Interval Timer mode 16-Bit Event Counter mode 16-Bit Programmable Pulse Generation (PPG) mode 2-Phase Pulse Input Counter mode (TMRB2 and TMRB3 only) Each channel has the capture capability used to latch the value of the counter. The capture capability allows: * * * Frequency measurement Pulse width measurement Time difference measurement The main components of a TMRBn block are a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, capture control logic, a timer flip-flop and its associated control logic. A total of thirteen registers provide control over the operating modes and timer flip-flops for each of the TMRB0 to TMRB3. Each channel is independently programmable and functionally equivalent except that the TMRB2 and TMRB3 support the 2-phase pulse count function. In the following sections, any references to the TMRB0 also apply to all the other channels. Table 12.1 gives the pins and registers for the four channels. Table 12.1 Pins and Registers for the TMRB0-TMRB3 Channel Specifications External Pins External clock/capture trigger inputs Capture trigger timer Timer flip-flop output Timer Run register Timer Control register Timer Mode register Timer Flip-Flop Control register Timer Status register Registers (Addresses) Timer registers TMRB0 TB0IN0 (shared with PL4) TB0IN1 (shared with PL5) TA3OUT TMRB1 TMRB2 TMRB3 TB1IN0 (shared with PL6) TB2IN0 (shared with PB2) TB3IN0 (shared with PB5) TB1IN1 (shared with PL7) TB2IN1 (shared with PB3) TB3IN1 (shared with PB6) TA3OUT TA3OUT TA3OUT TB0OUT (shared with PB0) TB1OUT (shared with PB1) TB2OUT (shared with PB4) TB3OUT (shared with PB7) TB0RUN (0xFFFF_F143) TB0CR (0xFFFF_F142) TB0MOD (0xFFFF_F141) TB1RUN (0xFFFF_F153) TB1CR (0xFFFF_F152) TB1MOD (0xFFFF_F151) TB2RUN (0xFFFF_F163) TB2CR (0xFFFF_F162) TB2MOD (0xFFFF_F161) TB3RUN (0xFFFF_F173) TB3CR (0xFFFF_F172) TB3MOD (0xFFFF_F171) TB0FFCR (0xFFFF_F140) TB1FFCR (0xFFFF_F150) TB2FFCR(0xFFFF_F160) TB3FFCR (0xFFFF_F170) TB0ST (0xFFFF_F147) TB1ST (0xFFFF_F157) TB2ST (0xFFFF_F167) TB3ST (0xFFFF_F177) TB0RG0L (0xFFFF_F14B) TB1RG0L (0xFFFF_F15B) TB2RG0L (0xFFFF_F16B) TB3RG0L (0xFFFF_F17B) TB0RG0H (0xFFFF_F14A) TB1RG0H (0xFFFF_F15A) TB2RG0H (0xFFFF_F16A) TB3RG0H (0xFFFF_F17A) TB0RG1L (0xFFFF_F149) TB1RG1L (0xFFFF_F159) TB2RG1L (0xFFFF_F169) TB3RG1L (0xFFFF_F179) TB0RG1H (0xFFFF_F148) TB1RG1H (0xFFFF_F158) TB2RG1H (0xFFFF_F168) TB3RG1H (0xFFFF_F178) TB0CP0L (0xFFFF_F14F) TB1CP0L (0xFFFF_F15F) TB2CP0L (0xFFFF_F16F) TB3CP0L (0xFFFF_F17F) Capture registers TB0CP0H (0xFFFF_F14E) TB1CP0H (0xFFFF_F15E) TB2CP0H (0xFFFF_F16E) TB3CP0H (0xFFFF_F17E) TB0CP1L (0xFFFF_F14D) TB1CP1L (0xFFFF_F15D) TB2CP1L (0xFFFF_F16D) TB3CP1L (0xFFFF_F17D) TB0CP1H (0xFFFF_F14C) TB1CP1H (0xFFFF_F15C) TB2CP1H (0xFFFF_F16C) TB3CP1H (0xFFFF_F17C) TMP1962-238 2006-02-21 Internal Data Bus Internal Data Bus 12.1 Block Diagrams Prescaler Clock Source: T0 2 T2 Capture Register 0 TB0CP0H/L TB0MOD run/ clear TB0RUN Timer Flip-Flop Output TB0OUT TA3OUT TB0IN0 TB0IN1 Capture Control Selector TB0MOD T0 (From TMRA23) Figure 12.1 TMRB0 Block Diagram (TMRB1 is similar to the above.) TMP1962-239 16-Bit Comparator (CP0) 16-Bit Timer Register TB0RG0H/L TB0RUN TMRB0 Interrupt INTTB0 Register 1 Interrupt Output Register 0 Interrupt Output Overflow Interrupt Output 16-Bit Timer Register TB0RG1H/L 16-Bit Timer Status Register TB0ST TMP1962C10BXBG Internal Data Bus 2006-02-21 Internal Data Bus Internal Data Bus Prescaler Clock Source: T0 2 T2 TB2MOD run/ clear TB2RUN Timer FlipFlop Output TB2OUT TA3OUT (From TMRA23) TB2IN0 TB2IN1 TMRB2 Interrupt INTTB2 Figure 12.2 TMRB2 Block Diagram (TMRB3 is similar to the above.) TMP1962-240 16-Bit Comparator (CP0) Match Detect 16-Bit Timer Register TB2RG0H/L TB2RUN Overflow Interrupt Output Up/Down Interrupt Output Underflow Interrupt Output Match Detect 16-Bit Comparator (CP1) 16-Bit Timer Register TB2RG1H/L TMP1962C10BXBG 16-Bit Timer Status Register TB2ST Register 1 Interrupt Output Register 0 Interrupt Output 2006-02-21 Internal Data Bus TMP1962C10BXBG 12.2 Timer Components 12.2.1 Prescaler The TMRB0 has a 5-bit prescaler that slows the rate of a clocking source to the counter. The prescaler clock source (T0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the TMRB0 prescaler. A write of 1 to this bit starts the prescaler. A write of 0 to this bit clears and halts the prescaler. Table 12.2 shows prescaler output clock resolutions. Table 12.2 Prescaler Output Clock Resolutions @fc = 40.5 MHz Peripheral Clock Select FPSEL Clock Gear Value GEAR[1:0] 00 (fc) Prescaler Clock Source PRCK[1:0] 00 (fperiph/16) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) Prescaler Output Clock Resolution T0 fc/2 (0.4 s) 4 T2 fc/2 (1.58 s) 6 8 7 6 9 8 7 T8 fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 fc/2 (0.2 s) 3 2 5 4 3 fc/2 (0.8 s) 5 4 fc/2 (0.1 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (1.58 s) 6 fc/2 (0.4 s) fc/2 (3.16 s) 7 6 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) fc/2 (1.58 s) fc/2 (0.8 s) 5 fc/2 (6.32 s) 8 7 6 9 8 7 6 fc/2 (0.8 s) 5 4 fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.8 s) 5 4 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (50.6 s) 11 10 9 8 7 6 8 7 6 8 7 6 8 7 6 fc/2 (0.4 s) fc/2 (3.16 s) 7 6 11 (fc/8) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) fc/2 (1.58 s) fc/2 (0.8 s) 5 4 3 2 4 3 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.4 s) 4 00 (fc) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) fc/2 (0.4 s) fc/2 (1.58 s) 6 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) 01 (fperiph/8) 10 (fperip/4) 00 (fperiph/16) fc/2 (0.8 s) 5 4 fc/2 (0.4 s) fc/2 (1.58 s) 6 fc/2 (0.8 s) 5 4 fc/2 (0.4 s) fc/2 (1.58 s) 6 11 (fc/8) 01 (fperiph/8) 10 (fperip/4) fc/2 (0.8 s) 5 Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The - character means "Setting prohibited." TMP1962-241 2006-02-21 TMP1962C10BXBG 12.2.2 Up-Counter (UC0) The TMRB0 contains a 16-bit binary up-counter, which is driven by a clock selected by the TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either one of three prescaler outputs (1, T4, T16) or the external clock applied to the TB0IN0 pin. The TB0RUN bit in the TB0RUN register is used to start the UC0 and to stop and clear the UC0. The UC0 is cleared to 0000H, if so enabled, when it reaches the value in the TB0RG1H/L register. The TB0CLE bit in the TB0MOD register allows the user to enable and disable this clearing. If it is disabled, the UC0 acts as a free-running counter. An overflow interrupt (INTTB01) is generated upon a counter overflow. The TMRB2 and TMRB3 support the 2-phase pulse input count function. Setting the TB2UDCE bit in the TR2RUN register to 1 selects 2-Phase Pulse Count mode, causing the TMRB2 to operate as an up/down counter, which is initialized to 0x7FFF. When the counter overflows, it is reloaded with 0x0000. When the counter underflows, it is reloaded with 0xFFFF. In other modes, the TMRB2 and TMRB3 only operate as up-counters. 12.2.3 Timer Registers (TB0RG0H/L and TB0RG1H/L) Each timer channel has two 16-bit timer registers containing a time constant. When the up-counter reaches the time constant value in each timer register, the associated comparator block generates a match-detect signal. Each of the timer registers (TB0RG0H/L, TB0RG1H/L) can be written with either a halfword-store instruction or a series of two byte-store instructions. When byte-store instructions are used, the low-order byte must be stored first, followed by the high-order byte. One of the two timer registers, TB0RG0, is double-buffered. The double-buffering function can be enabled and disabled through the programming of the TB0RDE bit in the TB0RUN: 0=disable, 1=enable. If double-buffering is enabled, the TB0RG0 latches a new time constant value from the register buffer. This takes place when a match is detected between the UC0 and the TB0RG1. Upon reset, the contents of the TB0RG0 and TB0RG1 are undefined; thus, they must be loaded with valid values before the timer can be used. A reset clears the TB0RUN.TB0RDE bit to 0, disabling the double-buffering function. To use this function, the TB0RUN.TB0RDE bit must be set to 1 after loading the TB0RG0 and TB0RG1 with time constants. When TB0RUN.TB0RDE=1, the next time constant can be written to the register buffer. The TB0RG0 and the corresponding register buffer are mapped to the same address (0xFFFF_F18A and 0xFFFF_F18B). When TB0RUN.TB0RDE = 0, a time constant value is written to both the TB0RG0 and the register buffer; when TB0RUN.TB0RDE = 1, a time constant value is written only to the register buffer. Therefore, the double-buffering function should be disabled when writing an initial time constant to the timer register. TMP1962-242 2006-02-21 TMP1962C10BXBG 12.2.4 Capture Registers (TB0CP0H/L and TB0CP1H/L) The capture registers are 16-bit registers used to latch the value of the up-counter (UC0). Each of the capture registers can be read with either a halfword-load instruction or a series of two byte-load instructions. When byte-load instructions are used, the low-order byte must be read first, followed by the high-order byte. 12.2.5 Capture Control Logic The capture control logic controls the capture of an up-counter (UC0) value into the capture registers (TB0CP0 and TB0CP1). The TB0CPM[1:0] field in the TB0MOD register selects a capture trigger input to be sensed by the capture control logic. Furthermore, a counter value can be captured under software control; a write of 0 to the TB0MOD.TB0CP0 bit causes the current UC0 value to be latched into the TB0CP0. To use the capture capability, the prescaler must be running (i.e., TB0RUN.TB0PRUN=1). In 2-Phase Pulse Count mode (for the TMRB2 and TMRB3 only), the counter value is captured under software control. Note 1: Reading the eight low-order bits of a capture register disables the capture capability. Reading the eight high-order bits thereafter re-enables the capture capability. Note 2: Do not stop the timer after only reading the eight low-order bits of a capture register. If this is done, the capture capability continues to remain in the disabled state even after the timer is restarted. 12.2.6 Comparators (CP0 and CP1) The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of the up-counter (UC0) with a time constant value in the TB0RG0. The CP1 block compares the output of the UC0 with a time constant value in the TB0RG1. When a match is detected, an interrupt (INTTB0) is generated. 12.2.7 Timer Flip-Flop (TB0FF0) The timer flip-flop (TB0FF0) is toggled, if so enabled, upon assertion of match-detect signals from the comparators and latch signals from the capture control logic. The toggling of the TB0FF0 can be enabled and disabled through the programming of the TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1 bits in the TB0FFCR register. Upon reset, the TB0FF0 assumes an undefined state. The TB0FF0 can be initialized to 1 or 0 by writing 01 or 10 to the TB0FF0C[1:0] field in the TB0FFCR. A write of 01 to this field sets the TB0FF0; a write of 10 to this field clears the TB0FF0. Additionally, a write of 00 causes the TB0FF0 to be toggled to the opposite value. The value of the TB0FF0 can be driven onto the TB0OUT pin, which is multiplexed with PB0. The Port B registers (PBCR and PBFC) must be programmed to configure the PB0/TB0OUT pin as TB0OUT. TMP1962-243 2006-02-21 TMP1962C10BXBG 12.3 Register Description TMRBn Run Register (n = 0 or 1) 7 TBnRUN (0xFFFF_ F1x3) Bit Symbol Read/Write Reset Value Function TBnRDE R/W 0 Doublebuffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 R/W 0 Must be written as 0. 3 I2TBn R/W 0 IDLE 0: Off 1: On 2 TBnPRUN R/W 0 1 0 TBnRUN R/W 0 Timer run/stop control 0: Stop & clear 1: Run TBnRUN: TBnPRUN: I2TBn: TBnRDE: Runs or stops the TMRBn. Runs or stops the TMRBn prescaler. Enables or disables the operation of the TMRBn in IDLE mode. Enables or disables double-buffering. Note: Bits 1 and 5 of the TBnRUN are read as 0. TMRBn Run Register (m = 2 or 3) 7 TBmRUN (0xFFFF_ F1x3) Bit Symbol Read/Write Reset Value Function TBmRDE R/W 0 Doublebuffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 UDmCK R/W 0 Must be written as 1. 4 TBmUDCE 3 I2TBm R/W 0 IDLE 0: Off 1: On 2 TBmPRUN 1 0 TBmRUN R/W 0 R/W 0 2-phase counter enable 0: Disable 1: Enable R/W 0 Timer run/stop control 0: Stop & clear 1: Run TBmRUN: TBmPRUN: I2TBm: TBmUDCE: UDmCK: TBmRDE: Runs or stops the TMRBm. Runs or stops the TMRBm prescaler. Enables or disables the operation of the TMRBm in IDLE mode. Enables or disables the 2-phase pulse input count function. Selects the sampling clock for the 2-phase pulse input count function. Enables or disables double-buffering. Note 1: Bit 1 of the TBmRUN is read as 0. Note 2: When bit 4 of the TBmRUN is set to 1, the TMRBm enters 2-Phase Pulse Input Count mode and the counter operates as an up/down counter. When the bit is cleared to 0, the TMRBm enters normal timer mode and the counter operates as an up-counter only. Figure 12.3 TMRB Registers TMP1962-244 2006-02-21 TMP1962C10BXBG TMRBn Control Register (n = 0 to 3) 7 TBnCR (0xFFFF_ F1x2) Bit Symbol Read/Write Reset Value Function TBnEN R/W 0 TMRBn operation 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 3 2 1 0 TBnEN: Enables or disables the operation of the TMRBn. If the TMRBn is disabled, no clock pulses are supplied to the TMRBn registers other than the TBnCR, so that power consumption in the system can be reduced (only the TBnCR can be read or written). To use the TMRBn, set the TBnEN bit to 1 before configuring other registers of the TMRBn. Once the TMRBn operates, all settings in its registers are held if it is disabled. Note: Bits 0 to 5 of the TBnCR are read as 0. TMRBn Mode Register (n = 0 to 3) 7 TBnMOD (0xFFFF_ F1x1) Bit Symbol Read/Write Reset Value Function 0 0 Must be written as 00. 6 5 TBnCP0 W 1 Software capture 0: Capture 1: Don't care 4 3 2 TBnCLE R/W 0 Upcounter clear control 0: Disable 1: Enable 1 TBnCLK1 0 Clock source 00: TBnIN0 input 01: T0 10: T2 11: T8 0 TBnCLK0 0 TBnCPM1 TBnCPM0 0 Capture triggers 00: Disabled 01: TBnIN0 TBnIN1 10: TBnIN0 TBnIN0 11: TA3OUT TA3OUT 0 TBnCLK[1:0]: Selects the clock source for the TMRBn. TBnCLE: 0: 1: Enables or disables the clearing of the TMRBn up-counter. Disables clearing. Enables the up-counter to be cleared upon a match with TBnRG1. TBnCPM[1:0]: Specifies the TMRBn capture timing. 00: Disables the capture function. 01: Latches the counter value into Capture Register 0 (TBnCP0) at rising edges of TBnIN0. Latches the counter value into Capture Register 1 (TBnCP1) at rising edges of TBnIN1. 10: Latches the counter value into Capture Register 0 (TBnCP0) at rising edges of TBnIN0. Latches the counter value into Capture Register 1 (TBnCP1) at falling edges of TBnIN0. 11: Latches the counter value into Capture Register 0 (TBnCP0) at rising edges of TA3OUT (8-bit timer match output). Latches the counter value into Capture Register 1 (TBnCP1) at falling edges of TA3OUT. TMRB0 to 3: TA3OUT TBnCP0: Writing 0 to this bit latches the counter value into Capture Register 0 (TBnCP0). Note: Bit 5 of the TBnMOD is read as 1. Figure 12.4 TMRB Registers TMP1962-245 2006-02-21 TMP1962C10BXBG TMRBn Flip-Flop Control Register (n = 0 to 3) 7 TBnFFCR (0xFFFF_ F1x0) Bit Symbol Read/Write Reset Value Function 1 6 5 TBnC1T1 0 4 TBnC0T1 0 R/W 3 TBnE1T1 0 2 TBnE0T1 0 1 W* 1 TBnFF0 control 00: Invert 01: Set 0 TBnFF0C1 TBnFF0C0 1 W* 1 Must be written as 11. * This field is always read as 11. TBnFF0 toggle trigger 0: Trigger disabled 1: Trigger enabled When the up-counter value is latched into TBnCP1 When the up-counter value is latched into TBnCP0 When the up-counter value reaches TBnRG1 When the 10: Clear up-counter 11: Don't care value * This field is always reaches read as 11. TBnRG0 TBnFF0C[1:0]: Controls the timer flip-flop. 00: Toggles TBnFF0. (software toggle) 01: Sets TBnFF0 to 1. 10: Clears TBnFF0 to 0. 11: Don't care. TBnE[1:0]: TBnC[1:0]: Enables or disables the toggling of the timer-flip flop when the up-counter value reaches the value stored in Timer Register 0 or 1 (TBnRG0/1). Enables or disables the toggling of the timer-flip flop when the up-counter value is latched into Capture Register 0 or 1 (TBnCP0/1). Figure 12.5 TMRB Registers TMP1962-246 2006-02-21 TMP1962C10BXBG TMRBn Status Register (n = 0 or 1) 7 TBnST (0xFFFF_ F1x7) Bit Symbol Read/Write Reset Value Function 0 6 5 4 3 2 INTTBOFn 1 INTTBn1 R 0 0 INTTBn0 0 0: No 0: No 0: No interrupt interrupt interrupt generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated INTTBn0: INTTBn1: INTTBOFn: Timer Register 0 (TBnRG0) match-detected interrupt Timer Register 1 (TBnRG1) match-detected interrupt Up-counter overflow interrupt Note: When an interrupt occurs, the corresponding flag in the TBnST is set and the INTC is notified of the interrupt. Reading the TBnST register results in all its flags being cleared. TMRBm Status Register (m = 2 or 3) (1) When TBmRUN.TBmUDCE = 0: Normal timer mode 7 TBmST (0xFFFF_ F1x7) Bit Symbol Read/Write Reset Value Function 0 6 5 4 3 2 INTTBOFm 1 INTTBm1 R 0 0 INTTBm0 0 0: No 0: No 0: No interrupt interrupt interrupt generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated INTTBm0: INTTBm1: INTTBOFm: Timer Register 0 (TBmRG0) match-detected interrupt Timer Register 1 (TBmRG1) match-detected interrupt Up-counter overflow interrupt Note: When an interrupt occurs, the corresponding flag in the TBmST is set and the INTC is notified of the interrupt. Reading the TBmST register results in all its flags being cleared. TMP1962-247 2006-02-21 TMP1962C10BXBG (2) When TBmRUN.TBmUDCE = 1: 2-Phase Pulse Input Count mode 7 TBmST (0xFFFF_ F1x7) Bit Symbol Read/Write Reset Value Function 0 Up/down count 0: No count cremented or decremented) 6 5 4 INTTBUDm 3 INTTBUDFm 2 INTTBOUFm 1 0 R 0 Underflow 0 Overflow 0: No 0: No underflow overflow 1: Count (in- 1: Underflow 1: Overflow INTTBOVFm: Up/down counter overflow interrupt INTTBUDFm: Up/down counter underflow interrupt INTTBUDm: Up- or down-count interrupt Note: When an interrupt occurs, the corresponding flag in the TBmST is set and the INTC is notified of the interrupt. Reading the TBmST register results in all its flags being cleared. Figure 12.6 TMRB Registers TMP1962-248 2006-02-21 TMP1962C10BXBG 12.4 Operating Modes 12.4.1 16-Bit Interval Timer Mode In the following example, the TMRB0 is used to accomplish periodic interrupt generation. The interval time is set in Timer Register 1 (TB0RG1), and the INTTB01 interrupt is enabled. 7 TB0RUN IMC7LH TB0FFCR TB0MOD TB0RG1 TB0RUN 0 X 1 0 * * 0 6 0 X 1 0 * * 0 5 X 1 0 1 * * X 4 0 1 0 0 * * 0 3 - 0 0 0 * * - 2 0 1 0 1 * * 1 1 X 0 1 * * * X 0 0 0 1 * * * 1 Stops the TMRB0. Enables INTTB0 and sets its priority level to 4. Disables the timer flip-flop toggle trigger. Selects a prescaler output clock as the timer clock source and disables the capture function. Sets the interval time (16 bits). Starts the TMRB0. (** = 01, 10, 11) X = Don't care, - = No change 12.4.2 16-Bit Event Counter Mode This mode is used to count events by interpreting the rising edges of the external counter clock (TB0IN0) as events. The up-counter counts up on each rising clock edge. The counter value can be latched into a capture register under software control. To determine the number of events (i.e., cycles) counted, the value in the capture register must be read. 7 TB0RUN PLCR PLFC IMC7LH TB0FFCR TB0MOD TB0RG1 TB0RUN 0 - - X 1 0 * 0 6 0 - - X 1 0 * 0 5 X - - 1 0 1 * X 4 0 0 1 1 0 0 * 0 3 - - - 0 0 0 * - 2 0 - - 1 0 1 * 1 1 X - - 0 1 0 * X 0 0 - - 0 1 0 * 1 Stops the TMRB0. Configures the PL4 pin for Input mode. Enables INTTB0 (interrupt level = 4). Disables the timer flip-flop toggle trigger. Selects the TB0IN0 input as the timer clock source. Sets a count value (16 bits). Starts the TMRB0. X = Don't care, - = No change Even when the timer is used for event counting, the prescaler must be programmed to run (i.e., the TB0RUN.TB0PRUN bit must be set to 1). TMP1962-249 2006-02-21 TMP1962C10BXBG 12.4.3 16-Bit Programmable Pulse Generation (PPG) Mode The 16-Bit PPG mode can be used to generate a square wave with any frequency and duty cycle. The pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (TB0FF). A square wave is generated by toggling the timer flip-flop every time the up-counter UC0 reaches the values in each timer register (TB0RG0 and TB0RG1). The square-wave output is driven to the TB0OUT pin. In this mode, the following relationship must be satisfied: (TB0RG0 value) < (TB0RG1 value) TB0RG0 Match (INTTB00 Interrupt) TB0RG1 Match (INTTB01 Interrupt) TB0OUT Pin Figure 12.7 PPG Output Waveform If the double-buffering function is enabled, the TB0RG0 value can be changed dynamically by writing a new value into the register buffer. Upon a match between the TB0RG1 and the UC0, the TB0RG0 latches a new value from the register buffer. The TB0RG0 can be loaded with a new value upon every match, thus making it easy to generate a square wave with virtually any duty cycle. TB0RG0 Match Up-Counter = Q1 TB0RG1 Match Shift into TB0RG1 TB0RG0 (Compare Value) Register Buffer Q1 Q2 Write to TB0RG0 Q2 Q3 Up-Counter = Q2 Figure 12.8 Register Buffer Operation TMP1962-250 2006-02-21 TMP1962C10BXBG Figure 12.9 shows a functional diagram of 16-Bit PPG mode. TB0RUN TB0IN0 T0 T2 T8 Selector Match 16-Bit Comparator 16-Bit Comparator Selector TB0RG0 TB0RG0-WR Register Buffer 0 TB0RUN Internal Data Bus Figure 12.9 Functional Diagram of 16-Bit PPG Mode The following is an example of running the timer in 16-Bit PPG mode. 7 TB0RUN TB0RG0 TB0RG1 TB0RUN 0 * * 1 6 0 * * 0 5 X * * X 4 0 * * 0 3 - * * - 2 0 * * 0 1 X * * X 0 0 * * 0 Disables the TB0RG0 double-buffering and stops the TMRB0. Defines the duty cycle (16 bits). Defines the cycle period (16 bits). Enables the TB0RG0 double-buffering. (The duty cycle and cycle period are changed by the INTTB01 interrupt.) TB0FFCR X X 0 0 1 1 1 0 Toggles the TB0FF0 when a match is detected between UC0 and TB0RG0 and between UC0 and TB0RG1. Initially clears the TB0FF0 to 0. Selects a prescaler output clock as the timer clock source and disables the capture function. - - 0 - - - - - 1 - - X 1 1 1 Configures the PB0 pin as TB0OUT. Starts the TMRB0. TB0MOD PBCR PBFC TB0RUN 0 - - 1 0 1 - - 0 0 1 * * (** = 01, 10, 11) 0 X X = Don't care, - = No change TMP1962-251 2006-02-21 TMP1962C10BXBG 12.4.4 Timing and Measurement Functions Using the Capture Capability The capture capability of the TMRBn provides versatile timing and measurement functions, including the following: (1) One-shot pulse generation using an external trigger pulse (2) Frequency measurement (3) Pulse width measurement (4) Time difference measurement * One-shot pulse generation using an external trigger pulse The TMRBn can be used to produce a one-time pulse as follows. The 16-bit up-counter (UC2) is programmed to function as a free-running counter, clocked by one of the prescaler outputs. The TB2IN0 pin is used as an active-high external trigger pulse input for latching the counter value into Capture Register 0 (TB2CP0). The Interrupt Controller (INTC) must be programmed to generate an INT5 interrupt upon detection of a rising edge on the TB2IN0 pin. A one-shot pulse has a delay and width controlled by the values stored in the timer registers (TB2RG0 and TB2RG1). Programming the TB2RG0 and TB2RG1 is the responsibility of the INT5 interrupt handler. The TB2RG0 is loaded with the sum of the TB2CP0 value (c) plus the pulse delay (d) - i.e., (c) + (d). The TB2RG1 is loaded with the sum of the TB2RG0 value plus the pulse width (p) - i.e., (c) + (d) + (p). Next, the TB2E1T1 and TB2E0T1 bits in the Timer Flip-Flop Control register (TB2FFCR) are set to 11, so that the timer flip-flop (TB2FF0) will toggle when a match is detected between the UC2 and the TB2RG0 and between the UC2 and the TB2RG1. With the TB2FF0 toggled twice, a one-shot pulse is produced. Upon a match between the UC2 and the TB2RG1, the TMRB2 generates the INTTB2 interrupt, which must disable the toggle trigger for the TB2FF0. Figure 12.10 depicts one-shot pulse generation, with annotations showing (c), (d) and (p). The counter is free-running. Counter Clock (Internal Clock) TB2IN0 Input Pin (External Trigger Pulse) c c+d c+d+p TB2RG0 Match The UC2 value is latched into TB2CP1. INT5 is generated. INTTB2 is generated. INTTB2 is generated. Toggle is enabled. TB2RG1 Match Toggle is enabled. Toggle is disabled for a capture into TB2CP1. Delay (d) TB2OUT (Timer Output) Pin Pulse Width (p) Figure 12.10 One-Shot Pulse Generation (with a Delay) TMP1962-252 2006-02-21 TMP1962C10BXBG Example: Generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an external trigger pulse on the TB2IN0 pin Clocking conditions: System clock: High-speed clock gear: Prescaler clock: Settings in the main routine Places the counter in Free-Running mode. 7 TB2MOD X 6 X 5 1 4 0 3 1 2 0 1 0 0 Selects T0 as the counter clock source. 1 Latches UC2 value into TB2CP0 at rising edges of the TB2IN0 input. TB2FFCR X X 0 0 0 0 1 0 Clears TB2FF0 to 0. Disables the toggle trigger for TB2FF0. PBCR PBFC IMC2HL IMCCLH TB2RUN - - X X - X X 0 - - 1 1 X 1 1 1 1 0 - - 0 0 - 1 0 1 - - 0 0 X - - 0 Enables INT5 and disables INTTB2. 0 1 Starts the TMRB2. Configures the PB4 pin as TB2OUT. High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) Settings in INT5 TB2RG0 TB2RG1 TB2FFCR TB0CP0 + 3ms/T1 TB0RG0 + 2ms/T1 X X - - 1 1 - - Enables the TB2FF0 toggle trigger for TB2RG0 and TB2RG1 matches. IMCCLH X X 1 1 0 1 0 0 Enables INTTB2. Settings in INTTB2 TB2FFCR X X - - 0 0 - - Disables the TB2FF0 toggle trigger for TB2RG0 and TB2RG1 matches. IMCCLH X X 1 1 0 0 0 0 Disables INTTB2. X = Don't care, - = No change If no delay is necessary, enable the TB2FF0 toggle trigger for a capture of the UC2 value into the TB2CP0. Use the INT5 interrupt to load the TB2RG1 with a sum of the TB2CP0 value (c) plus the pulse width (p) and to enable the TB2FF0 toggle trigger for a match between the UC2 and TB2RG1 values. A match generates the INTTB2 interrupt, which then is to disable the TB2FF0 toggle trigger. TMP1962-253 2006-02-21 TMP1962C10BXBG Counter Clock (Prescaler Output Clock) TB2IN0 Input (External Trigger Pulse) c c+p The UC2 value is latched into TB2CP0. INT5 is generated. INTTB2 is generated. TB2RG1 Match Toggle is enabled. TB2OUT (Timer Output) Pin Pulse Width Toggle is enabled for a capture into TB2CP0. (p) Toggle is left disabled for a capture into TB2CP1 so that it will not be toggled. The UC2 value is latched into TB2CP1. Figure 12.11 One-Shot Pulse Generation (without a Delay) * Frequency measurement The capture function can be used to measure the frequency of an external clock. Frequency measurement requires a 16-bit TMRBn channel running in Event Counter mode and the 8-bit TMRA01. The timer flip-flop (TA1FF) in the TMRA01 is used to define the duration during which a measurement is taken. Select the TB0IN0 pin as the clock source for the TMRB0. Set the TB0CPM[1:0] field in the TB0MOD to 11 to select the TA1FF output signal from the TMRA01 as a capture trigger input. This causes the TMRB0 to latch the 16-bit up-counter (UC0) value into Capture Register 0 (TB0CP0) on the low-to-high transition of the TA1FF and into Capture Register 1 (TB0CP1) on the next high-to-low transition of the TA1FF. Either the INTTA0 or INTTA1 interrupt generated by the 8-bit timer can be used to make a frequency calculation. Counter Clock (TB0IN0 Input) C1 TA1OUT C2 Capture into TB0CP0 Capture into TB0CP1 INTTA0/INTTA1 C1 C2 C1 C2 Figure 12.12 Frequency Measurement For example, if the TA1FF of the 8-bit timer is programmed to be at logic 1 for a period of 0.5 seconds and the difference between the values captured into the TB0CP0 and TB0CP1 is 100, then the TB0IN0 frequency is calculated as 100 / 0.5 s = 200 Hz. TMP1962-254 2006-02-21 TMP1962C10BXBG * Pulse width measurement The capture function can be used to measure the pulse width of an external clock. The external clock is applied to the TB2IN0 pin. The up-counter (UC2) is programmed to operate as a free-running counter, clocked by one of the prescaler outputs. The capture function is used to latch the UC2 value into Capture Register 0 (TB2CP0) at the clock rising edge and into Capture Register 1 (TB2CP1) at the next clock falling edge. An INT5 interrupt is generated at the falling edge of the TB2IN0 input. Multiplying the counter clock period by the difference between the values captured into the TB2CP0 and TB2CP1 gives the high pulse width of the TB2IN0 clock. For example, if the prescaler output clock has a period of 0.5 s and the difference between the TB2CP0 and TB2CP1 is 100, the high pulse width is calculated as 0.5 s x 100 = 50 s. Measuring a pulse width exceeding the maximum counting time for the UC2, which depends on the clock source, requires software programming. Prescaler Output Clock TB2IN0 Input (External Clock) Capture into TB2CP0 Capture into TB2CP1 INT5 C1 C2 C1 C2 C1 C2 Figure 12.13 Pulse Width Measurement The low pulse width can be measured by the second INT5 interrupt. This is accomplished by multiplying the counter clock period by the difference between the TB2CP0 value at the first C2 and the TB2CP1 value at the second C1. TMP1962-255 2006-02-21 TMP1962C10BXBG * Time difference measurement The capture function can be used to measure the time difference between two event occurrences. The 16-bit up-counter (UC2) is programmed to operate as a free-running counter. The UC2 value is latched into Capture Register 0 (TB2CP0) on the rising edge of TB2IN0. An INT5 interrupt is generated at this time. Then, the UC2 value is latched into Capture Register 1 (TB2CP1) on the rising edge of TB2IN1. An INT6 interrupt is generated at this time. The time difference between the two events that occurred on the TB2IN0 and TB2IN1 pins is calculated by multiplying the counter clock period by the difference between the TB2CP1 and TB2CP0 values. Prescaler Output Clock C1 TB2IN0 Input TB2IN1 Input Capture into TB2CP0 C2 Capture into TB2CP1 INT5 INT6 Time Difference Figure 12.14 Time Difference Measurement TMP1962-256 2006-02-21 TMP1962C10BXBG 12.4.5 2-Phase Pulse Input Count Mode (TMRB2 and TMRB3) The TMRB2 and TMRB3 are functionally equivalent. This section only describes the TMRB2. In 2-Phase Pulse Input Count mode, the counter operates as an up/down counter that increments and decrements according to transitions in the states of 2-phase clocks, input through the TB2IN0 and TB2IN1 pins. An interrupt occurs when the counter increments or decrements, or when it overflows or underflows. (1) Count operation * Increment Counter value n+1 TB0IN0 0 1 TB0IN1 1 1 Counter value incremented by one Figure 12.15 When the Counter Increments * Decrement Counter value n n-1 TB0IN0 1 1 TB0IN1 0 1 Counter value decremented by one Figure 12.16 When the Counter Decrements TMRB2 Run Register (TB2RUN) 7 Bit Symbol Read/Write Reset Value Function TB2RDE R/W 0 Doublebuffering 0: Disable 1: Enable 6 5 UD2CK R/W 0 Sampling clock 4 TB2UDCE R/W 0 2-phase counter enable 3 I2TB2 R/W 0 IDLE 0: Off 1: On 2 TB2PRUN R/W 0 1 0 TB2RUN R/W 0 Timer run/stop control 0: Stop & clear 1: Run (count up) 0: Setting prohibited 0: Disable 1: fsys/2 1: Enable Figure 12.17 2-Phase Pulse Input Count Mode Register TMP1962-257 2006-02-21 TMP1962C10BXBG Setting the bit 5 (UD2CK) of the TB2RUN register to 1 specifies the sampling clock frequency. UD2CK (sampling clock) = 1 : fsys/2 (fsys/8-Hz sampling) Exiting STOP mode When the TMP1962 enters STOP mode, the 2-phase counter holds the current status. If the combination of the held status and the status of inputs used for terminating STOP mode satisfies the increment or decrement conditions, the counter increments or decrements when the TMP1962 exits STOP mode. If a fixed status is required after recovery from STOP mode, initialize the 2-phase counter to 0x7FFF once the TMP1962 exits STOP mode, by clearing the TB2RUN.TB2UCDE bit to 0 and then re-setting it to 1. (2) Operating mode Whether external signals input through the TB2IN0 and TB2IN1 pins are directed to the regular 16-bit timer (capture input) or the up/down counter depends on register settings. * * * In up/down counter mode, only software capture is available. The timer cannot capture data based on external clock timing. In up/down counter mode, the comparator is disabled; comparison with the timer register is not performed. Input clock sampling is based clock (system clock). The maximum input frequency is fsys/16 Hz . Enabling the up/down counter Clear the TB2CLK[0:1] bits of the TB2MOD register to 00, thus turning the prescaler off. Then, use bit 4 (TB2UDCE) of the TB2RUN register to specify whether the counter will operate as an up/down counter or a normal up-counter. TB2UDCE (up/down counter enable) = 0: Normal 16-bit timer operation = 1: Up/down counter operation TMRB2 Run Register (TB2RUN) 7 Bit Symbol Read/Write Reset Value Function TB2RDE R/W 0 Doublebuffering 0: Disable 1: Enable 6 5 UD2CK R/W 0 Sampling clock 4 TB2UDCE R/W 0 2-phase counter enable 3 I2TB2 R/W 0 IDLE 0: Off 1: On 2 TB2PRUN R/W 0 1 0 TB2RUN R/W 0 Timer run/stop control 0: Stop & clear 1: Run (count up) 0: Setting prohibited 0: Disable 1: fsys/2 1: Enable Figure 12.18 Up/Down Counter Enable Bit TMP1962-258 2006-02-21 TMP1962C10BXBG (3) Interrupts * NORMAL mode Enable the INTTB2 interrupt in the Interrupt Controller (INTC). An INTTB2 interrupt occurs when the counter increments or decrements. The interrupt service routine can read the TMRB2 status register (TB2ST) to determine whether an overflow or underflow has occurred. If an overflow occurs, the INTTBOUF2 bit of the TB2ST register is set to 1. If an underflow occurs, the INTTBUDF2 bit of the TB2ST register is set to 1. Reading the TB2ST register clears all of its bits. An overflow causes the counter value to be 0x0000 and an underflow causes the counter value to be 0xFFFF. In either case, counting continues. 7 TB2ST (0xFFFF_ F167) Bit Symbol Read/Write Reset Value Function 6 5 4 3 R 2 1 0 INTTBUD2 INTTBUDF2 INTTBOUF2 0 Up/down count 0: No count cremented or decremented) 0 Underflow 0 Overflow 0: No 0: No overflow underflow 1: Count (in- 1: Underflow 1: Overflow Figure 12.19 TMRB2 Status Register * STOP mode In STOP mode, the 2-phase pulse input counter is stopped. Enable the INT5 or INT6 for STOP wake-up signaling in the Clock Generator (CG). When the counter increments or decrements, an INT5 or INT6 interrupt occurs, causing the TMP1962 to exit STOP mode. Upon recovery from STOP mode, the TMP1962 enters NORMAL or SLOW mode after a specified warm-up time, restarting the counter. If the combination of the held status and the status of inputs used for terminating STOP mode satisfies the increment or decrement conditions, the counter increments or decrements. TMP1962-259 2006-02-21 TMP1962C10BXBG (4) Up/down counter When 2-Phase Pulse Input Count mode is selected (TB2RUN.TB2UCDE = 1), the up-counter operates as an up/down counter and is initialized to 0x7FFF. When the counter overflows, it is reset to 0x0000 and continues counting. When the counter underflows, it is reset to 0xFFFF and continues counting. Once an interrupt occurs, the interrupt service routine can determine the overflow or underflow status by reading the counter value and the status flags in the TB2ST. Sampling Clock Increment Input Up/Down Counter Value 0x3FFF 0x4000 0x4001 Up/Down Counter Interrupt Note 1: The increment or decrement input must be high before and after effective input. Note 2: The counter value must be read in the INTTB2 interrupt service routine. If it is read in the INT5 or INT6 interrupt routine used for STOP wake-up signaling, the value may vary depending on whether the increment/decrement conditions are satisfied or on the delay between recovery from STOP mode and the start of counting. TMP1962-260 2006-02-21 TMP1962C10BXBG 13. 32-Bit Input Capture (TMRC) The TMP1962 contains a 32-bit input capture circuit block (TMRC), which consists of a 1-channel 32-bit time base timer (TBT), eight 32-bit input capture registers (TCCAP0-TCCAP7) and eight 32-bit compare registers (TCCMP0-TCCMP7). Figure 13.1 shows a block diagram of the TMRC. 13.1 TMRC Block Diagram Prescaler Clock Source (T0) 2 4 8 16 32 64 128 256 RUN & Clear T1 T2 T4 T8 T16 T32 T64 T128 Clear & Count Control TBTIN (PM0) Noise Eliminator 32-Bit Time Base Timer (TBT) Prescaler Output (T0-T128) Capture Registers 0-7 (TCCAP0-TCCAP7) Overflow Interrupt (INTTBT) TC0IN (PM1) Noise Eliminator Edge Detection 32-Bit Input Capture (TCCAP0) Capture 0 Interrupt (INTCAP0) Compare Registers 0-7 (TCCMP0-TCCMP7) 32-Bit Comparator Compare Match Interrupt 0 (INTCMP0) Compare Match Trigger (CMP0TRG) Compare Match Output (TCOUT0) 32-Bit Register Buffer 0 32-Bit Compare Register 0 (TCCMP0) Figure 13.1 TMRC Block Diagram TMP1962-261 2006-02-21 TMP1962C10BXBG 13.2 Timer Components 13.2.1 Prescaler The TMRC has an 8-bit prescaler that slows the rate of a clocking source to the timer. The prescaler clock source (T0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The TBTPRUN bit in the TBTRUN register allows the enabling and disabling of the prescaler for the TMRC. A write of 1 to this bit starts the prescaler. A write of 0 to this bit clears and halts the prescaler. Table 13.1 shows prescaler output clock resolutions. Table 13.1 Prescaler Output Clock Resolutions @fc = 40.5 MHz Peripheral Clock Prescaler Clock Clock Gear Source Source Value PRCK[1:0] FPSEL GEAR[1:0] 0(fgear) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 1(fc) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 5 Prescaler Output Clock Resolution T1 fc/2 (0.79 s) 5 4 3 6 5 4 7 6 5 8 7 6 5 4 3 5 4 3 5 4 T2 fc/2 (1.58 s) 6 5 4 7 6 5 8 7 6 9 8 7 6 5 4 6 5 4 6 5 4 6 5 T4 fc/2 (3.16 s) 7 6 5 8 7 6 9 8 7 T8 fc/2 (6.32 s) 8 7 6 9 8 7 fc/2 (0.40 s) fc/2 (0.20 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (0.20 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (0.20 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (0.79 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (0.40 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 7 6 5 7 6 5 7 6 5 7 6 5 fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (50.6 s) 11 10 9 8 7 6 8 7 6 8 7 6 8 7 6 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (0.79 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (1.58 s) TMP1962-262 2006-02-21 TMP1962C10BXBG @fc = 40.5 MHz Peripheral Clock Prescaler Clock Clock Gear Source Source Value PRCK[1:0] FPSEL GEAR[1:0] 0(fgear) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 1(fc) 00(fc) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 01(fc/2) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 10(fc/4) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 11(fc/8) 00(fperiph/16) 01(fperiph/8) 10(fperiph/4) 9 8 7 Prescaler Output Clock Resolution T16 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (25.3 s) 10 9 8 10 9 8 T32 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (50.6 s) 11 10 9 11 10 9 T64 fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (101 s) 12 11 10 13 12 11 14 13 12 11 10 9 12 11 10 13 12 11 14 13 12 15 14 13 12 11 10 12 11 10 12 11 10 12 11 10 T128 fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (405 s) fc/2 (202 s) fc/2 (101 s) fc/2 (809 s) fc/2 (405 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (50.6 s) 11 10 9 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (101 s) 12 11 10 13 12 11 10 9 8 fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (405 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (50.6 s) 11 10 9 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (101 s) 12 11 10 9 8 7 9 8 7 9 8 7 9 8 7 fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (202 s) fc/2 (101 s) fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (25.3 s) 10 9 8 fc/2 (50.6 s) fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (3.16 s) fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (25.3 s) 10 9 8 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (50.6 s) 11 10 9 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (25.3 s) 10 9 8 fc/2 (25.3 s) fc/2 (12.6 s) fc/2 (50.6 s) 11 10 9 fc/2 (12.6 s) fc/2 (6.32 s) fc/2 (25.3 s) fc/2 (12.6 s) Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The - character means "Setting prohibited." TMP1962-263 2006-02-21 TMP1962C10BXBG 13.2.2 Noise Eliminator The noise eliminator removes noise components from the external clock source (TBTIN) and capture trigger input (TCnIN) for the time base timer (TBT). It can also output the input signals as is, without eliminating noise. 13.2.3 32-Bit Time Base Timer (TBT) The TMRC contains a 32-bit binary counter, which counts up on the rising edge of a clock selected by the TBTCLK[3:0] field in the TBT Control Register (TBTCR). The clock input to the TBT is either one of eight prescaler outputs (1, T2, 4, T8, 16, T32, 64, T128) or the external clock applied to the TBTIN pin. The TBTRUN bit in the TBTRUN register is used to start the TBT and to stop and clear the TBT. Upon reset, the TBT is cleared and stopped. When started, the TBT acts as a free-running counter. An overflow interrupt (INTTBT) is generated upon a counter overflow and clears the counter to 0, after which the counter restarts counting. INTTBT is grouped with other interrupt sources and controlled in the TCG1ST and TCG1IM registers, in the same way as INTCAPn described in Section 13.2.5. 13.2.4 Edge Detection Circuit This circuit samples the external capture input (TCnIN) and detects its edges. The CPnEG[1:0] field in the Capture Control Register (CAPnCR) defines the edge detection polarity: rising edge, falling edge, both edges or no capture. Figure 13.2 shows the relationship between the capture input and the output from the edge detection circuit (capture source output). TCnIN input Capture Source (When Rising Edges are Detected) (When Falling Edges are Detected) (When Both Edges are Detected) (When the Input is Not Captured) Figure 13.2 Capture Input and Capture Source Output (Output from the Edge Detection Circuit) TMP1962-264 2006-02-21 TMP1962C10BXBG 13.2.5 32-Bit Capture Registers The TMRC contains 32-bit registers to which the TBT counter value is captured in response to a capture trigger source. A capture interrupt (INTCAPn) occurs when the counter value is captured. INTCAP0 to INTCAP3 are handled as a group so that any of the four interrupt sources are sent to the INTC as the same interrupt source. The interrupt service routine can determine the actual source by reading the status register (TCG0ST). Unnecessary interrupt requests can be masked by setting corresponding bits in the interrupt mask register (TCG0IM). Any capture trigger does not cause the counter value to be captured while the capture register is being read. 13.2.6 32-Bit Compare Registers The TMRC contains eight 32-bit registers (TCCMP0-TCCMP7) in which compare values are stored. When the TBT value reaches the value stored in a compare register, the comparator activates the corresponding match-detected signal. The CMPEN[1:0] field in the Compare Control Register (CMPCTL) allows the enabling and disabling of comparison. TCCMPn can be written with either a word-store instruction, a series of two halfword-store instructions or a series of four byte-store instructions. When halfword-store or byte-store instructions are used, the low-order byte must be stored first, followed by the high-order byte. Each of the compare registers (TCCMPn) is double-buffered with Register Buffer n. The double-buffering function can be enabled and disabled through the programming of the CMPRDEn bit in the CMPCTL register: 0 = disable, 1 = enable. If double-buffering is enabled, the TCCMPn latches a new compare value from Register Buffer n. This takes place when a match is detected between the TBT and the TCCMPn. Upon reset, the contents of the TCCMPn are undefined; thus, they must be loaded with valid values before the timer can be used. A reset clears the CMPCTL.CMPRDEn bit to 0, disabling the double-buffering function. To use this function, the CMPCTL.CMPRDEn bit must be set to 1 after loading the TCCMPn with compare values. When CMPCTL.CMPRDEn = 1, the next compare value can be written to Register Buffer n. The TCCMPn and the corresponding register buffer are mapped to the same address. When CMPCTL.CMPRDEn = 0, a compare value is written to both the TCCMPn and the register buffer; when CMPCTL.CMPRDEn = 1, a compare value is written only to the register buffer. Therefore, the double-buffering function should be disabled when writing an initial compare value to a compare register. TMP1962-265 2006-02-21 TMP1962C10BXBG 13.3 Register Description TMRC Control Register 7 TCCR (0xFFFF_F403) Bit Symbol Read/Write Reset Value Function 0 TMRC operation 0: Disable 1: Enable TCEN R/W 0 IDLE 0: Off 1: On 6 I2TBT 5 4 3 2 1 0 I2TBT: TCEN: Enables or disables the operation of the TMRC in IDLE mode. Enables or disables the operation of the TMRC. If the TMRC is disabled, no clock pulses are supplied to the TMRC registers other than the TCCR, so that power consumption in the system can be reduced (only the TCCR can be read or written). To use the TMRC, set the TCEN bit to 1 before configuring other registers of the TMRC. Once the TMRC operates, all settings in its registers are held if it is disabled. Note: Bits 0 to 6 of the TCCR are read as 0. TBTRUN Register 7 TBTRUN (0xFFFF_F402) Bit Symbol Read/Write Reset Value Function 0 Must be written as 0. 6 5 4 3 2 TBTCAP W 0 TBT counter soft capture 0: Don't care 1: Soft capture 1 TBTPRUN 0 TBTRUN 0 R/W 0 0: Stop & clear 1: Run Timer run/stop control TBTRUN: TBTPRUN: TBTCAP: Runs or stops the TBT. Runs or stops the TBT prescaler. Setting this bit to 1 causes the TBT counter value to be captured into the capture register (TBTCAPn). Figure 13.3 TMRC Registers TMP1962-266 2006-02-21 TMP1962C10BXBG TBT Control Register 7 TBTCR (0xFFFF_F401) Bit Symbol Read/Write Reset Value Function 0 TBTIN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 R/W 3 TBTCLK3 2 TBTCLK2 0 0001: T2 0100: T16 0111: T128 1 TBTCLK1 0 0010: T4 0101: T32 0 TBTCLK0 0 TBTNF 0 0 0 0 0000: T1 0011: T8 0110: T64 Must be written as 0. TBT clock source 1xxx: TBTIN input TBTCLK[3:0]: Selects the TBT clock source. When TBTCLK[3:0] = 0000 to 0111, a prescaler output is used. When TBTCLK[3:0] = 1xxx, a clock input through the TBTIN pin is used. TBTNF: Controls whether noise will be eliminated from the signal input through the TBTIN pin. When TBTNF = 0, the TBTIN input is directly used as the TBT clock source. When TBTNF = 1, high and low levels on TBTIN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. TBT Capture Register (TBTCAP) 31 TBTCAP3 (0xFFFF_F404) Bit Symbol Read/Write Reset Value Function Capture data CAP031 30 CAP030 29 CAP029 28 CAP028 R 27 CAP027 26 CAP026 25 CAP025 24 CAP024 23 TBTCAP2 (0xFFFF_F405) Bit Symbol Read/Write Reset Value Function CAP023 22 CAP022 21 CAP021 20 CAP020 R 19 CAP019 18 CAP018 17 CAP017 16 CAP016 Capture data 15 TBTCAP1 (0xFFFF_F406) Bit Symbol Read/Write Reset Value Function CAP015 14 CAP014 13 CAP013 12 CAP012 R 11 CAP011 10 CAP010 9 CAP09 8 CAP08 Capture data 7 TBTCAP0 (0xFFFF_F407) Bit Symbol Read/Write Reset Value Function CAP07 6 CAP06 5 CAP05 4 CAP04 R 3 CAP03 2 CAP02 1 CAP01 0 CAP00 Capture data Figure 13.4 TMRC Registers TMP1962-267 2006-02-21 TMP1962C10BXBG TMRC Capture 0 Control Register 7 CAP0CR (0xFFFF_F413) Bit Symbol Read/Write Reset Value Function TC0NF R/W 0 TC0IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP0EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP0EG0 0 TC0IN edge detection CP0EG[1:0]: TC0NF: Selects the edge to be detected on the TC0IN pin for the TCCAP0. When CP0EG[1:0] = 00, capture is disabled for the TCCAP0. Controls whether noise will be eliminated from the signal input through the TC0IN pin. When TC0NF = 0, the TC0IN input is directly used as the TCCAP0 trigger input. When TC0NF = 1, high and low levels on TC0IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP0CR are read as 0. Figure 13.5 TMRC Registers TMP1962-268 2006-02-21 TMP1962C10BXBG TMRC Capture 0 Register (TCCAP0) 31 TCCAP0HH (0xFFFF_F414) Bit Symbol Read/Write Reset Value Function Capture 0 data CAP031 30 CAP030 29 CAP029 28 CAP028 R 27 CAP027 26 CAP026 25 CAP025 24 CAP024 23 TCCAP0HL (0xFFFF_F415) Bit Symbol Read/Write Reset Value Function CAP023 22 CAP022 21 CAP021 20 CAP020 R 19 CAP019 18 CAP018 17 CAP017 16 CAP016 Capture 0 data 15 TCCAP0LH (0xFFFF_F416) Bit Symbol Read/Write Reset Value Function CAP015 14 CAP014 13 CAP013 12 CAP012 R 11 CAP011 10 CAP010 9 CAP09 8 CAP08 Capture 0 data 7 TCCAP0LL (0xFFFF_F417) Bit Symbol Read/Write Reset Value Function CAP07 6 CAP06 5 CAP05 4 CAP04 R 3 CAP03 2 CAP02 1 CAP01 0 CAP00 Capture 0 data Note 1: Upon reset, the contents of the TCCAP0 are undefined. Note 2: The counter value is not captured while the capture register is being read. TMRCG0 Interrupt Mask Register 7 TCG0IM (0xFFFF_F40B) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 TCIM3 2 TCIM2 R/W 1 TCIM1 0 0 TCIM0 0 1: Masks 1: Masks 1: Masks 1: Masks INTCAP3. INTCAP2. INTCAP1. INTCAP0. Note: Bits 4, 5, 6 and 7 of the TCG0IM are read as 0. TMRCG0 Status Register 7 TCG0ST (0xFFFF_F40A) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 3 INTCAP3 2 INTCAP2 R 1 INTCAP1 0 0 INTCAP0 0 0: No 0: No 0: No 0: No interrupt interrupt interrupt interrupt generated generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated generated Note 1: Reading the TCG0ST register results in bits 0, 1, 2 and 3 being cleared. Note 2: Bits 4, 5, 6 and 7 of the TCG0ST are read as 0. Figure 13.6 TMRC Registers TMP1962-269 2006-02-21 TMP1962C10BXBG TMRC Capture 1 Control Register 7 CAP1CR (0xFFFF_F41B) Bit Symbol Read/Write Reset Value Function TC1NF R/W 0 TC1IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP1EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP1EG0 0 TC1IN edge detection CP1EG[1:0]: TC1NF: Selects the edge to be detected on the TC1IN pin for the TCCAP1. When CP1EG[1:0] = 00, capture is disabled for the TCCAP1. Controls whether noise will be eliminated from the signal input through the TC1IN pin. When TC1NF = 0, the TC1IN input is directly used as the TCCAP1 trigger input. When TC1NF = 1, high and low levels on TC1IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP1CR are read as 0. TMRC Capture 1 Register (TCCAP1) 31 TCCAP1HH (0xFFFF_F41C) Bit Symbol Read/Write Reset Value Function Capture 1 data CAP131 30 CAP130 29 CAP129 28 CAP128 R 27 CAP127 26 CAP126 25 CAP125 24 CAP124 23 TCCAP1HL (0xFFFF_F41D) Bit Symbol Read/Write Reset Value Function CAP123 22 CAP122 21 CAP121 20 CAP120 R 19 CAP119 18 CAP118 17 CAP117 16 CAP116 Capture 1 data 15 TCCAP1LH (0xFFFF_F41E) Bit Symbol Read/Write Reset Value Function CAP115 14 CAP114 13 CAP113 12 CAP112 R 11 CAP111 10 CAP110 9 CAP19 8 CAP18 Capture 1 data 7 TCCAP1LL (0xFFFF_F41F) Bit Symbol Read/Write Reset Value Function CAP17 6 CAP16 5 CAP15 4 CAP14 R 3 CAP13 2 CAP12 1 CAP11 0 CAP10 Capture 1 data Note 1: Upon reset, the contents of the TCCAP1 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.7 TMRC Registers TMP1962-270 2006-02-21 TMP1962C10BXBG TMRC Capture 2 Control Register 7 CAP2CR (0xFFFF_F423) Bit Symbol Read/Write Reset Value Function TC2NF R/W 0 TC2IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP2EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP2EG0 0 TC2IN edge detection CP2EG[1:0]: TC2NF: Selects the edge to be detected on the TC2IN pin for the TCCAP2. When CP2EG[1:0] = 00, capture is disabled for the TCCAP2. Controls whether noise will be eliminated from the signal input through the TC2IN pin. When TC2NF = 0, the TC2IN input is directly used as the TCCAP2 trigger input. When TC2NF = 1, high and low levels on TC2IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP2CR are read as 0. TMRC Capture 2 Register (TCCAP2) 31 TCCAP2HH (0xFFFF_F424) Bit Symbol Read/Write Reset Value Function Capture 2 data CAP231 30 CAP230 29 CAP229 28 CAP228 R 27 CAP227 26 CAP226 25 CAP225 24 CAP224 23 TCCAP2HL (0xFFFF_F425) Bit Symbol Read/Write Reset Value Function CAP223 22 CAP222 21 CAP221 20 CAP220 R 19 CAP219 18 CAP218 17 CAP217 16 CAP216 Capture 2 data 15 TCCAP2LH (0xFFFF_F426) Bit Symbol Read/Write Reset Value Function CAP215 14 CAP214 13 CAP213 12 CAP212 R 11 CAP211 10 CAP210 9 CAP29 8 CAP28 Capture 2 data 7 TCCAP2LL (0xFFFF_F427) Bit Symbol Read/Write Reset Value Function CAP27 6 CAP26 5 CAP25 4 CAP24 R 3 CAP23 2 CAP22 1 CAP21 0 CAP20 Capture 2 data Note 1: Upon reset, the contents of the TCCAP2 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.8 TMRC Registers TMP1962-271 2006-02-21 TMP1962C10BXBG TMRC Capture 3 Control Register 7 CAP3CR (0xFFFF_F42B) Bit Symbol Read/Write Reset Value Function TC3NF R/W 0 TC3IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP3EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP3EG0 0 TC3IN edge detection CP3EG[1:0]: TC3NF: Selects the edge to be detected on the TC3IN pin for the TCCAP3. When CP3EG[1:0] = 00, capture is disabled for the TCCAP3. Controls whether noise will be eliminated from the signal input through the TC3IN pin. When TC3NF = 0, the TC3IN input is directly used as the TCCAP3 trigger input. When TC3NF = 1, high and low levels on TC3IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP3CR are read as 0. TMRC Capture 3 Register (TCCAP3) 31 TCCAP3HH (0xFFFF_F42C) Bit Symbol Read/Write Reset Value Function Capture 3 data CAP331 30 CAP330 29 CAP329 28 CAP328 R 27 CAP327 26 CAP326 25 CAP325 24 CAP324 23 TCCAP3HL (0xFFFF_F42D) Bit Symbol Read/Write Reset Value Function CAP323 22 CAP322 21 CAP321 20 CAP320 R 19 CAP319 18 CAP318 17 CAP317 16 CAP316 Capture 3 data 15 TCCAP3LH (0xFFFF_F42E) Bit Symbol Read/Write Reset Value Function CAP315 14 CAP314 13 CAP313 12 CAP312 R 11 CAP311 10 CAP310 9 CAP39 8 CAP38 Capture 3 data 7 TCCAP3LL (0xFFFF_F42F) Bit Symbol Read/Write Reset Value Function CAP37 6 CAP36 5 CAP35 4 CAP34 R 3 CAP33 2 CAP32 1 CAP31 0 CAP30 Capture 3 data Note 1: Upon reset, the contents of the TCCAP3 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.9 TMRC Registers TMP1962-272 2006-02-21 TMP1962C10BXBG TMRC Capture 4 Control Register 7 CAP4CR (0xFFFF_F433) Bit Symbol Read/Write Reset Value Function TC4NF R/W 0 TC4IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP4EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP4EG0 0 TC4IN edge detection CP4EG[1:0]: TC4NF: Selects the edge to be detected on the TC4IN pin for the TCCAP4. When CP4EG[1:0] = 00, capture is disabled for the TCCAP4. Controls whether noise will be eliminated from the signal input through the TC4IN pin. When TC4NF = 0, the TC4IN input is directly used as the TCCAP4 trigger input. When TC4NF = 1, high and low levels on TC4IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP4CR are read as 0. TMRC Capture 4 Register (TCCAP4) 31 TCCAP4HH (0xFFFF_F434) Bit Symbol Read/Write Reset Value Function Capture 4 data CAP431 30 CAP430 29 CAP429 28 CAP428 R 27 CAP427 26 CAP426 25 CAP425 24 CAP424 23 TCCAP4HL (0xFFFF_F435) Bit Symbol Read/Write Reset Value Function CAP423 22 CAP422 21 CAP421 20 CAP420 R 19 CAP419 18 CAP418 17 CAP417 16 CAP416 Capture 4 data 15 TCCAP4LH (0xFFFF_F436) Bit Symbol Read/Write Reset Value Function CAP415 14 CAP414 13 CAP413 12 CAP412 R 11 CAP411 10 CAP410 9 CAP49 8 CAP48 Capture 4 data 7 TCCAP4LL (0xFFFF_F437) Bit Symbol Read/Write Reset Value Function CAP47 6 CAP46 5 CAP45 4 CAP44 R 3 CAP43 2 CAP42 1 CAP41 0 CAP40 Capture 4 data Note 1: Upon reset, the contents of the TCCAP4 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.10 TMRC Registers TMP1962-273 2006-02-21 TMP1962C10BXBG TMRCG1 Interrupt Mask Register 7 TCG1IM (0xFFFF_F409) Bit Symbol Read/Write Reset Value Function 0 1: Masks INTTBT. 6 5 4 TBTIM 3 TCIM7 0 2 TCIM6 R/W 0 1 TCIM5 0 0 TCIM4 0 1: Masks 1: Masks 1: Masks 1: Masks INTCAP7. INTCAP6. INTCAP5. INTCAP4. Note: Bits 5, 6 and 7 of the TCG1IM are read as 0. TMRCG1 Status Register 7 TCG1ST (0xFFFF_F408) Bit Symbol Read/Write Reset Value Function 0 0 6 5 4 INTTBT 3 INTCAP7 2 INTCAP6 R 0 1 INTCAP5 0 0 INTCAP4 0 0: No 0: No 0: No 0: No 0: No interrupt interrupt interrupt interrupt interrupt generated generated generated generated generated 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt 1: Interrupt generated generated generated generated generated Note 1: Reading the TCG1ST register results in bits 0, 1, 2, 3 and 4 being cleared. Note 2: Bits 5, 6 and 7 of the TCG1ST are read as 0. Figure 13.11 TMRC Registers TMP1962-274 2006-02-21 TMP1962C10BXBG TMRC Capture 5 Control Register 7 CAP5CR (0xFFFF_F43B) Bit Symbol Read/Write Reset Value Function TC5NF R/W 0 TC5IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP5EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP5EG0 0 TC5IN edge detection CP5EG[1:0]: TC5NF: Selects the edge to be detected on the TC5IN pin for the TCCAP5. When CP5EG[1:0] = 00, capture is disabled for the TCCAP5. Controls whether noise will be eliminated from the signal input through the TC5IN pin. When TC5NF = 0, the TC5IN input is directly used as the TCCAP5 trigger input. When TC5NF = 1, high and low levels on TC5IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP5CR are read as 0. TMRC Capture 5 Register (TCCAP5) 31 TCCAP5HH (0xFFFF_F43C) Bit Symbol Read/Write Reset Value Function Capture 5 data CAP531 30 CAP530 29 CAP529 28 CAP528 R 27 CAP527 26 CAP526 25 CAP525 24 CAP524 23 TCCAP5HL (0xFFFF_F43D) Bit Symbol Read/Write Reset Value Function CAP523 22 CAP522 21 CAP521 20 CAP520 R 19 CAP519 18 CAP518 17 CAP517 16 CAP516 Capture 5 data 15 TCCAP5LH (0xFFFF_F43E) Bit Symbol Read/Write Reset Value Function CAP515 14 CAP514 13 CAP513 12 CAP512 R 11 CAP511 10 CAP510 9 CAP59 8 CAP58 Capture 5 data 7 TCCAP5LL (0xFFFF_F43F) Bit Symbol Read/Write Reset Value Function CAP57 6 CAP56 5 CAP55 4 CAP54 R 3 CAP53 2 CAP52 1 CAP51 0 CAP50 Capture 5 data Note 1: Upon reset, the contents of the TCCAP5 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.12 TMRC Registers TMP1962-275 2006-02-21 TMP1962C10BXBG TMRC Capture 6 Control Register 7 CAP6CR (0xFFFF_F443) Bit Symbol Read/Write Reset Value Function TC6NF R/W 0 TC6IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP6EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP6EG0 0 TC6IN edge detection CP6EG[1:0]: TC6NF: Selects the edge to be detected on the TC6IN pin for the TCCAP6. When CP6EG[1:0] = 00, capture is disabled for the TCCAP6. Controls whether noise will be eliminated from the signal input through the TC6IN pin. When TC6NF = 0, the TC6IN input is directly used as the TCCAP6 trigger input. When TC6NF = 1, high and low levels on TC6IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP6CR are read as 0. TMRC Capture 6 Register (TCCAP6) 31 TCCAP6HH (0xFFFF_F444) Bit Symbol Read/Write Reset Value Function Capture 6 data CAP631 30 CAP630 29 CAP629 28 CAP628 R 27 CAP627 26 CAP626 25 CAP625 24 CAP624 23 TCCAP6HL (0xFFFF_F445) Bit Symbol Read/Write Reset Value Function CAP623 22 CAP622 21 CAP621 20 CAP620 R 19 CAP619 18 CAP618 17 CAP617 16 CAP616 Capture 6 data 15 TCCAP6LH (0xFFFF_F446) Bit Symbol Read/Write Reset Value Function CAP615 14 CAP614 13 CAP613 12 CAP612 R 11 CAP611 10 CAP610 9 CAP69 8 CAP68 Capture 6 data 7 TCCAP6LL (0xFFFF_F447) Bit Symbol Read/Write Reset Value Function CAP67 6 CAP66 5 CAP65 4 CAP64 R 3 CAP63 2 CAP62 1 CAP61 0 CAP60 Capture 6 data Note 1: Upon reset, the contents of the TCCAP6 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.13 TMRC Registers TMP1962-276 2006-02-21 TMP1962C10BXBG TMRC Capture 7 Control Register 7 CAP7CR (0xFFFF_F44B) Bit Symbol Read/Write Reset Value Function TC7NF R/W 0 TC7IN input noise elimination 0: Not eliminated 1: Eliminated 6 5 4 3 2 1 CP7EG1 0 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges R/W 0 CP7EG0 0 TC7IN edge detection CP7EG[1:0]: TC7NF: Selects the edge to be detected on the TC7IN pin for the TCCAP7. When CP7EG[1:0] = 00, capture is disabled for the TCCAP7. Controls whether noise will be eliminated from the signal input through the TC7IN pin. When TC7NF = 0, the TC7IN input is directly used as the TCCAP7 trigger input. When TC7NF = 1, high and low levels on TC7IN shorter than 4/fsys (99 ns @fperiph = fc = 40.5 MHz) are regarded as noise and eliminated from the input. The elimination threshold varies with the clock gear setting. Note: Bits 2 to 6 of the CAP7CR are read as 0. TMRC Capture 7 Register (TCCAP7) 31 TCCAP7HH (0xFFFF_F44C) Bit Symbol Read/Write Reset Value Function Capture 7 data CAP731 30 CAP730 29 CAP729 28 CAP728 R 27 CAP727 26 CAP726 25 CAP725 24 CAP724 23 TCCAP7HL (0xFFFF_F44D) Bit Symbol Read/Write Reset Value Function CAP723 22 CAP722 21 CAP721 20 CAP720 R 19 CAP719 18 CAP718 17 CAP717 16 CAP716 Capture 7 data 15 TCCAP7LH (0xFFFF_F44E) Bit Symbol Read/Write Reset Value Function CAP715 14 CAP714 13 CAP713 12 CAP712 R 11 CAP711 10 CAP710 9 CAP79 8 CAP78 Capture 7 data 7 TCCAP7LL (0xFFFF_F44F) Bit Symbol Read/Write Reset Value Function CAP77 6 CAP76 5 CAP75 4 CAP74 R 3 CAP73 2 CAP72 1 CAP71 0 CAP70 Capture 7 data Note 1: Upon reset, the contents of the TCCAP7 are undefined. Note 2: The counter value is not captured while the capture register is being read. Figure 13.14 TMRC Registers TMP1962-277 2006-02-21 TMP1962C10BXBG TMRC Compare Control Register (CMPCTL) 31 CMPCTL7 (0xFFFF_F474) Bit Symbol Read/Write Reset Value Function 0 30 TCFFEN7 R/W 0 TCFF7 toggle trigger 0: Disable 1: Enable 29 TCFFC71 W 1 TCFF7 control 00: Toggle 01: Set 10: Clear 11: Don't care 28 TCFFC70 1 27 26 25 CMPRDE7 24 CMPEN7 0 R/W 0 0 0 Double-bu Compare 7 ffering 7 0: Disable 0: Disable 1: Enable 1: Enable 23 CMPCTL6 (0xFFFF_F475) Bit Symbol Read/Write Reset Value Function 0 22 TCFFEN6 R/W 0 TCFF6 toggle trigger 0: Disable 1: Enable 21 TCFFC61 W 1 TCFF6 control 00: Toggle 01: Set 10: Clear 11: Don't care 20 TCFFC60 1 19 18 17 CMPRDE6 16 CMPEN6 0 R/W 0 0 0 Double-bu Compare 6 ffering 6 0: Disable 0: Disable 1: Enable 1: Enable 15 CMPCTL5 (0xFFFF_F476) Bit Symbol Read/Write Reset Value Function 0 14 TCFFEN5 R/W 0 TCFF5 toggle trigger 0: Disable 1: Enable 13 TCFFC51 W 1 TCFF5 control 00: Toggle 01: Set 10: Clear 11: Don't care 12 TCFFC50 1 11 10 9 CMPRDE5 8 CMPEN5 0 R/W 0 0 0 Double-bu Compare 5 ffering 5 0: Disable 0: Disable 1: Enable 1: Enable 7 CMPCTL4 (0xFFFF_F477) Bit Symbol Read/Write Reset Value Function 0 6 TCFFEN4 R/W 0 TCFF4 toggle trigger 0: Disable 1: Enable 5 TCFFC41 W 1 TCFF4 control 00: Toggle 01: Set 10: Clear 11: Don't care 4 TCFFC40 1 3 2 1 CMPRDE4 0 CMPEN4 0 R/W 0 0 0 Double-bu Compare 4 ffering 4 0: Disable 0: Disable 1: Enable 1: Enable TMP1962-278 2006-02-21 TMP1962C10BXBG TMRC Compare Control Register (CMPCTL) 31 CMPCTL3 (0xFFFF_F470) Bit Symbol Read/Write Reset Value Function 0 30 TCFFEN3 R/W 0 TCFF3 toggle trigger 0: Disable 1: Enable 29 TCFFC31 W 1 TCFF3 control 00: Toggle 01: Set 10: Clear 11: Don't care 28 TCFFC30 1 27 26 25 CMPRDE3 24 CMPEN3 0 R/W 0 0 0 Double-bu Compare 3 ffering 3 0: Disable 0: Disable 1: Enable 1: Enable 23 CMPCTL2 (0xFFFF_F471) Bit Symbol Read/Write Reset Value Function 0 22 TCFFEN2 R/W 0 TCFF2 toggle trigger 0: Disable 1: Enable 21 TCFFC21 W 1 TCFF2 control 00: Toggle 01: Set 10: Clear 11: Don't care 20 TCFFC20 1 19 18 17 CMPRDE2 16 CMPEN2 0 R/W 0 0 0 Double-bu Compare 2 ffering 2 0: Disable 0: Disable 1: Enable 1: Enable 15 CMPCTL1 (0xFFFF_F472) Bit Symbol Read/Write Reset Value Function 0 14 TCFFEN1 R/W 0 TCFF1 toggle trigger 0: Disable 1: Enable 13 TCFFC11 W 1 TCFF1 control 00: Toggle 01: Set 10: Clear 11: Don't care 12 TCFFC10 1 11 10 9 CMPRDE1 8 CMPEN1 0 R/W 0 0 0 Double-bu Compare 1 ffering 1 0: Disable 0: Disable 1: Enable 1: Enable 7 CMPCTL0 (0xFFFF_F473) Bit Symbol Read/Write Reset Value Function 0 6 TCFFEN0 R/W 0 TCFF0 toggle trigger 0: Disable 1: Enable 5 TCFFC01 W 1 TCFF0 control 00: Toggle 01: Set 10: Clear 11: Don't care 4 TCFFC00 1 3 2 1 CMPRDE0 0 CMPEN0 0 R/W 0 0 0 Double-bu Compare 0 ffering 0 0: Disable 0: Disable 1: Enable 1: Enable CMPENn: CMPRDEn: TCFFENn: Enables or disables the detection of a match in comparison. Enables or disables double-buffering for the compare register. Enables or disables the toggling of the compare match output flip-flop. TCFFCn[1:0]: Controls the compare match output flip-flop. Note: Bits 31, 27, 26, 23, 19, 18, 15, 11, 10, 7, 3 and 2 of the CMPTCL are read as 0. Figure 13.15 TMRC Registers TMP1962-279 2006-02-21 TMP1962C10BXBG TMRC Compare Register 0 (TCCMP0) 31 TCCMP0HH (0xFFFF_F450) Bit Symbol Read/Write Reset Value Function Compare register 0 data CMP031 30 CMP030 29 CMP029 28 CMP028 W 27 CMP027 26 CMP026 25 CMP025 24 CMP024 23 TCCMP0HL (0xFFFF_F451) Bit Symbol Read/Write Reset Value Function CMP023 22 CMP022 21 CMP021 20 CMP020 W 19 CMP019 18 CMP018 17 CMP017 16 CMP016 Compare register 0 data 15 TCCMP0LH (0xFFFF_F452) Bit Symbol Read/Write Reset Value Function CMP015 14 CMP014 13 CMP013 12 CMP012 W 11 CMP011 10 CMP010 9 CMP09 8 CMP08 Compare register 0 data 7 TCCMP0LL (0xFFFF_F453) Bit Symbol Read/Write Reset Value Function CMP07 6 CMP06 5 CMP05 4 CMP04 W 3 CMP03 2 CMP02 1 CMP01 0 CMP00 Compare register 0 data Note: The TCCMP0 is a write-only register. Upon reset, its contents are undefined. TMRC Compare Register 1 (TCCMP1) 31 TCCMP1HH (0xFFFF_F454) Bit Symbol Read/Write Reset Value Function Compare register 1 data CMP131 30 CMP130 29 CMP129 28 CMP128 W 27 CMP127 26 CMP126 25 CMP125 24 CMP124 23 TCCMP1HL (0xFFFF_F455) Bit Symbol Read/Write Reset Value Function CMP123 22 CMP122 21 CMP121 20 CMP120 W 19 CMP119 18 CMP118 17 CMP117 16 CMP116 Compare register 1 data 15 TCCMP1LH (0xFFFF_F456) Bit Symbol Read/Write Reset Value Function CMP115 14 CMP114 13 CMP113 12 CMP112 W 11 CMP111 10 CMP110 9 CMP19 8 CMP18 Compare register 1 data 7 TCCMP1LL (0xFFFF_F457) Bit Symbol Read/Write Reset Value Function CMP17 6 CMP16 5 CMP15 4 CMP14 W 3 CMP13 2 CMP12 1 CMP11 0 CMP10 Compare register 1 data Note: The TCCMP1 is a write-only register. Upon reset, its contents are undefined. Figure 13.16 TMRC Registers TMP1962-280 2006-02-21 TMP1962C10BXBG TMRC Compare Register 2 (TCCMP2) 31 TCCMP2HH (0xFFFF_F458) Bit Symbol Read/Write Reset Value Function Compare register 2 data CMP231 30 CMP230 29 CMP229 28 CMP228 W 27 CMP227 26 CMP226 25 CMP225 24 CMP224 23 TCCMP2HL (0xFFFF_F459) Bit Symbol Read/Write Reset Value Function CMP223 22 CMP222 21 CMP221 20 CMP220 W 19 CMP219 18 CMP218 17 CMP217 16 CMP216 Compare register 2 data 15 TCCMP2LH (0xFFFF_F45A) Bit Symbol Read/Write Reset Value Function CMP215 14 CMP214 13 CMP213 12 CMP212 W 11 CMP211 10 CMP210 9 CMP29 8 CMP28 Compare register 2 data 7 TCCMP2LL (0xFFFF_F45B) Bit Symbol Read/Write Reset Value Function CMP27 6 CMP26 5 CMP25 4 CMP24 W 3 CMP23 2 CMP22 1 CMP21 0 CMP20 Compare register 2 data Note: The TCCMP2 is a write-only register. Upon reset, its contents are undefined. TMRC Compare Register 3 (TCCMP3) 31 TCCMP3HH (0xFFFF_F45C) Bit Symbol Read/Write Reset Value Function Compare register 3 data CMP331 30 CMP330 29 CMP329 28 CMP328 W 27 CMP327 26 CMP326 25 CMP325 24 CMP324 23 TCCMP3HL (0xFFFF_F45D) Bit Symbol Read/Write Reset Value Function CMP323 22 CMP322 21 CMP321 20 CMP320 W 19 CMP319 18 CMP318 17 CMP317 16 CMP316 Compare register 3 data 15 TCCMP3LH (0xFFFF_F45E) Bit Symbol Read/Write Reset Value Function CMP315 14 CMP314 13 CMP313 12 CMP312 W 11 CMP311 10 CMP310 9 CMP39 8 CMP38 Compare register 3 data 7 TCCMP3LL (0xFFFF_F45F) Bit Symbol Read/Write Reset Value Function CMP37 6 CMP36 5 CMP35 4 CMP34 W 3 CMP33 2 CMP32 1 CMP31 0 CMP30 Compare register 3 data Note: The TCCMP3 is a write-only register. Upon reset, its contents are undefined. Figure 13.17 TMRC Registers TMP1962-281 2006-02-21 TMP1962C10BXBG TMRC Compare Register 4 (TCCMP4) 31 TCCMP4HH (0xFFFF_F460) Bit Symbol Read/Write Reset Value Function Compare register 4 data CMP431 30 CMP430 29 CMP429 28 CMP428 W 27 CMP427 26 CMP426 25 CMP425 24 CMP424 23 TCCMP4HL (0xFFFF_F461) Bit Symbol Read/Write Reset Value Function CMP423 22 CMP422 21 CMP421 20 CMP420 W 19 CMP419 18 CMP418 17 CMP417 16 CMP416 Compare register 4 data 15 TCCMP4LH (0xFFFF_F462) Bit Symbol Read/Write Reset Value Function CMP415 14 CMP414 13 CMP413 12 CMP412 W 11 CMP411 10 CMP410 9 CMP49 8 CMP48 Compare register 4 data 7 TCCMP4LL (0xFFFF_F463) Bit Symbol Read/Write Reset Value Function CMP47 6 CMP46 5 CMP45 4 CMP44 W 3 CMP43 2 CMP42 1 CMP41 0 CMP40 Compare register 4 data Note: The TCCMP4 is a write-only register. Upon reset, its contents are undefined. TMRC Compare Register 5 (TCCMP5) 31 TCCMP5HH (0xFFFF_F464) Bit Symbol Read/Write Reset Value Function Compare register 5 data CMP531 30 CMP530 29 CMP529 28 CMP528 W 27 CMP527 26 CMP526 25 CMP525 24 CMP524 23 TCCMP5HL (0xFFFF_F465) Bit Symbol Read/Write Reset Value Function CMP523 22 CMP522 21 CMP521 20 CMP520 W 19 CMP519 18 CMP518 17 CMP517 16 CMP516 Compare register 5 data 15 TCCMP5LH (0xFFFF_F466) Bit Symbol Read/Write Reset Value Function CMP515 14 CMP514 13 CMP513 12 CMP512 W 11 CMP511 10 CMP510 9 CMP59 8 CMP58 Compare register 5 data 7 TCCMP5LL (0xFFFF_F467) Bit Symbol Read/Write Reset Value Function CMP57 6 CMP56 5 CMP55 4 CMP54 W 3 CMP53 2 CMP52 1 CMP51 0 CMP50 Compare register 5 data Note: The TCCMP5 is a write-only register. Upon reset, its contents are undefined. Figure 13.18 TMRC Registers TMP1962-282 2006-02-21 TMP1962C10BXBG TMRC Compare Register 6 (TCCMP6) 31 TCCMP6HH (0xFFFF_F468) Bit Symbol Read/Write Reset Value Function Compare register 6 data CMP631 30 CMP630 29 CMP629 28 CMP628 W 27 CMP627 26 CMP626 25 CMP625 24 CMP624 23 TCCMP6HL (0xFFFF_F469) Bit Symbol Read/Write Reset Value Function CMP623 22 CMP622 21 CMP621 20 CMP620 W 19 CMP619 18 CMP618 17 CMP617 16 CMP616 Compare register 6 data 15 TCCMP6LH (0xFFFF_F46A) Bit Symbol Read/Write Reset Value Function CMP615 14 CMP614 13 CMP613 12 CMP612 W 11 CMP611 10 CMP610 9 CMP69 8 CMP68 Compare register 6 data 7 TCCMP6LL (0xFFFF_F46B) Bit Symbol Read/Write Reset Value Function CMP67 6 CMP66 5 CMP65 4 CMP64 W 3 CMP63 2 CMP62 1 CMP61 0 CMP60 Compare register 6 data Note: The TCCMP6 is a write-only register. Upon reset, its contents are undefined. TMRC Compare Register 7 (TCCMP7) 31 TCCMP7HH (0xFFFF_F46C) Bit Symbol Read/Write Reset Value Function Compare register 7 data CMP731 30 CMP730 29 CMP729 28 CMP728 W 27 CMP727 26 CMP726 25 CMP725 24 CMP724 23 TCCMP7HL (0xFFFF_F46D) Bit Symbol Read/Write Reset Value Function CMP723 22 CMP722 21 CMP721 20 CMP720 W 19 CMP719 18 CMP718 17 CMP717 16 CMP716 Compare register 7 data 15 TCCMP7LH (0xFFFF_F46E) Bit Symbol Read/Write Reset Value Function CMP715 14 CMP714 13 CMP713 12 CMP712 W 11 CMP711 10 CMP710 9 CMP79 8 CMP78 Compare register 7 data 7 TCCMP7LL (0xFFFF_F46F) Bit Symbol Read/Write Reset Value Function CM77 6 CMP76 5 CMP75 4 CMP74 W 3 CMP73 2 CMP72 1 CMP71 0 CMP70 Compare register 7 data Note: The TCCMP7 is a write-only register. Upon reset, its contents are undefined. Figure 13.19 TMRC Registers TMP1962-283 2006-02-21 TMP1962C10BXBG 14. Serial I/O (SIO) The TMP1962 serial I/O contains seven channels (SIO0-SIO6). Each serial channel provides Universal Asynchronous Receiver/Transmitter (UART) mode and synchronous I/O Interface mode. * I/O Interface mode Mode 0: Mode 1: * UART mode Mode 2: Mode 3: Transmits/receives a serial clock (SCLK) as well as data streams for a synchronous clock mode of operation. 7 data bits 8 data bits 9 data bits In Mode 1 and Mode 2, each frame can include a parity bit. In Mode 3, an SIO channel operates in a wakeup mode for multidrop applications in which a master station is connected to several slave stations through a serial link. Figure 14.2 shows a block diagram of the SIO0. The main components of an SIO channel are a clock prescaler, a serial clock generator, a receive buffer, a receive controller, a transmit buffer and a transmit controller. Each SIO channel is independently programmable, and functionally equivalent. In the following sections, any references to the SIO0 also apply to the other channels. * Mode 0 (I/O Interface Mode): LSB first bit 0 1 2 3 4 5 6 7 Goes out first * Mode 0 (I/O Interface Mode): MSB first bit 7 6 5 4 3 2 1 0 Goes out first * Mode 1 (7-Bit UART Mode) Without parity start bit 0 1 2 3 4 5 6 stop With parity start bit 0 1 2 3 4 5 6 parity stop * Mode 2 (8-Bit UART Mode) Without parity start bit 0 1 2 3 4 5 6 7 stop With parity start bit 0 1 2 3 4 5 6 7 parity stop * Mode 3 (9-Bit UART Mode) start bit 0 1 2 3 4 5 6 7 8 stop start bit 0 1 2 3 4 5 6 7 bit 8 Stop (wake-up) Bit 8: Address/data bit flag 1: Address frame (select code) 0: Data frame Figure 14.1 Data Formats TMP1962-284 2006-02-21 TMP1962C10BXBG 14.1 Block Diagram (Channel 0) Prescaler 4 8 16 32 64 T0 2 T2 T8 T32 Serial Clock Generator BR0CR TABOUT (from TMRAB) Selector Selector UART Mode SIOCLK fSYS/2 BR0CR SC0MOD0 SC0MOD0 SCLK0 Input (Shared with PC2) I/O Interface Mode SCLK0 Output (Shared with PC2) I/O Interface Mode SC0CR INTRX0 Interrupt Request INTTX0 Interrupt Request Transmit Counter (/16 for UART) TXDCLK Transmit Control CTS0 Receive Counter (/16 for UART) RXDCLK SC0MOD0 SC0MOD0 Serial Channel SC0CR Parity Control (Shared with PC2) SC0MOD0 RXD0 (Shared with PC1) Receive Buffer 1 (Shift Register) RB8 Receive Buffer 2 (SC0BUF) Error Flag TB8 Transmit Buffer 2 (SC0BUF) SC0CR Figure 14.2 SIO Block Diagram TMP1962-285 2006-02-21 TMP1962C10BXBG 14.2 SIO Components (Channel 0) 14.2.1 Prescaler The SIO0 has a 6-bit prescaler that slows the rate of a clocking source to the serial clock generator. The prescaler clock source (T0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the PRCK[1:0] field of the SYSCR located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The serial clock is selectable from several clocks; the prescaler is only enabled when the baud rate generator output clock is selected as a serial clock. Table 14.1 shows prescaler output clock resolutions. Table 14.1 Prescaler Output Clock Resolutions @ = 40.5 MHz Peripheral Clock Select FPSEL Clock Gear Value GEAR[1:0] Prescaler Clock Source PRCK[1:0] 00 (fperiph/16) 00 (fc) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 11 (fc/8) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 00 (fc) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 01 (fperiph/8) 10 (fperiph/4) 00 (fperiph/16) 11 (fc/8) 01 (fperiph/8) 10 (fperiph/4) 4 Prescaler Output Clock Resolution T0 fc/2 (0.4 s) 4 3 2 5 4 3 6 5 4 7 6 5 4 3 2 4 3 T2 fc/2 (1.6 s) 6 5 4 7 6 5 8 7 6 T8 fc/2 (6.3 s) 8 7 6 T32 fc/2 (25.3 s) 10 9 fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.4 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (6.3 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (12.6s) fc/2 (6.3 s) 8 9 fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (12.6s) fc/2 (6.3 s) 8 7 9 fc/2 (12.6s) fc/2 (6.3 s) 8 11 fc/2 (50.6s) fc/2 (25.3 s) 10 9 fc/2 (3.2 s) fc/2 (25.3 s) 10 9 fc/2 (12.6s) fc/2 (101 s) 12 11 fc/2 (12.6s) fc/2 (6.3 s) 8 11 fc/2 (50.6s) fc/2 (25.3 s) 10 13 12 fc/2 (50.6s) fc/2 (25.3 s) 10 9 fc/2 (202s) fc/2 (101s) fc/2 (50.6s) fc/2 (25.3 s) 10 9 11 fc/2 (3.2 s) 7 fc/2 (12.6s) fc/2 (6.3 s) 8 7 6 8 7 6 8 7 6 8 7 6 fc/2 (1.6 s) 6 5 4 6 5 4 6 5 4 6 5 fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (6.3 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (6.3 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (6.3 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (12.6s) fc/2 (6.3 s) 8 fc/2 (25.3 s) 10 9 fc/2 (12.6s) fc/2 (6.3 s) 8 fc/2 (25.3 s) 10 9 fc/2 (12.6s) fc/2 (6.3 s) 8 fc/2 (25.3 s) 10 9 fc/2 (12.6s) fc/2 (6.3 s) 8 Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the SIO0 is operating. Note 3: The - character means "Setting prohibited. Prescaler output taps can be divide-by-1 (T0), divide-by-4 (T2), divide-by-16 (T8) and divide-by-64 (T32). TMP1962-286 2006-02-21 TMP1962C10BXBG 14.2.2 Baud rate generator The frequency used to transmit and receive data through the SIO0 is derived from the baud rate generator. The clock source for the baud rate generator can be selected from the 6-bit prescaler outputs (T0, T2, T8, T32) through the programming of the BR0CK[1:0] field in the BR0CR. The baud rate generator contains a clock divider that can divide the selected clock by 1, N + (m/16), or 16 (where N is an integer between 2 and 15, and m is an integer between 0 and 15). The clock divisor is programmed into the BR0ADDE and BR0S[3:0] bits in the BR0CR and the BR0K[3:0] bits in the BR0ADD. * UART mode (1) When BR0CR.BR0ADDE = 0 When the BR0CR.BR0ADDE bit is cleared, the BR0ADD.BR0K[3:0] field has no meaning or effect. In this case, the baud rate generator input clock is divided down by a value of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field. (2) When BR0CR.BR0ADDE = 1 Setting the BR0CR.BR0ADDE bit enables the N + (16 - K)/16 clock division function. The baud rate generator input clock is divided down according to the value of N (2 to 15) programmed in the BR0CR.BR0S[3:0] field and the value of K (1 to 15) programmed in the BR0ADD.BR0K[3:0] field. Note: Setting N to 1 or 16 disables the N + (16 - K)/16 clock division function. When N = 1 or 16, the BR0CR.BR0ADDE bit must be cleared. * I/O Interface mode I/O Interface mode cannot utilize the N + (16 - K)/16 clock division function. The BR0CR.BR0ADDE must be cleared, so the baud rate generator input clock is divided down by a value of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field. * Baud rate calculations (1) UART mode Baud rate = baud rate generator input clock / baud rate generator divisor / 16 When the clock input to the baud rate generator is 10.125-MHz T0, the maximum baud rate is 632.8 kbps. The baud rate generator can be bypassed if the user wants to use the fsys/2 clock as a serial clock. In this case, the maximum baud rate is 1.266 Mbps @fsys = 40.5 MHz. TMP1962-287 2006-02-21 TMP1962C10BXBG (2) I/O Interface mode Baud rate = baud rate generator input clock / baud rate generator divisor / 2 When the clock input to the baud rate generator is 10.125-MHz T0, the maximum baud rate is 5.06 Mbps (with no clock division by the baud rate generator) if double-buffering is used, or 2.53 Mbps (with the clock divided by 2 by the baud rate generator) if double-buffering is not used. * Calculation examples (1) Integral clock division (divide-by-N) fperiph = 40.5-MHz fc T0 = fperiph/16 Baud rate generator input clock: T2 Clock divisor N (BR0CR.BR0S[3:0]) = 4 BR0CR.BR0ADDE = 0 Clocking conditions System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/16 (fperiph = fsys) The baud rate in UART mode is determined as follows: Baud rate = (fc/64)/4 / 16 = 40.5 x 106 / 64 / 4 / 16 = 9888 (bps) Note: Clearing the BR0CR.BR0ADDE bit to 0 disables the N + (16 - K)/16 clock division function. At this time, the BR0ADD.BR0K[3:0] field is ignored. (2) N + (16 - K)/16 clock division (UART mode only) fperiph = 19.2-MHz fc T0 = fperiph/16 Baud rate generator input clock: T2 N (BR0CR.BR0S[3:0]) = 4 K (BR0ADD.BR0K[3:0]) = 14 BR0CR.BR0ADDE = 1 Clocking conditions System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) The baud rate is determined as follows: Baud Rate = (fc/64)/(4 + (16-14)/16) / 16 = 40.5 x 106 / 64 / (4 + 2/16) / 16 = 9588 (bps) TMP1962-288 2006-02-21 TMP1962C10BXBG The SIO0 can use an external clock as a serial clock, bypassing the baud rate generator. When an external clock is used, the baud rate is determined as shown below. * Using an external clock as a serial clock (1) UART mode Baud rate = external clock input / 16 The external clock period must be greater than or equal to 4/fsys. Therefore, when fsys =40.5 MHz, the maximum baud rate is 632.8 kbps (40.5 / 4 / 16). (2) I/O Interface mode Baud rate = external clock input clock When double-buffering is used, the external clock period must be greater than 12/fsys. Therefore, when fsys = 40.5 MHz, the maximum baud rate is 3.375 Mbps (40.5 / 12). When double-buffering is not used, the external clock period must be greater than 16/fsys. Therefore, when fsys = 40.5 MHz, the maximum baud rate is 2.53 Mbps (40.5 / 16). Table 14.2 and Table 14.3 show the UART baud rates obtained with various combinations of clock inputs and clock divisor values. TMP1962-289 2006-02-21 TMP1962C10BXBG Table 14.2 UART Baud Rate Selection (When the baud rate generator is used and BR0CR.BR0ADDE = 0) Baud Rate Generator Input Clock fc [MHz] 19.6608 24.576 29.4912 Unit: kbps T32 (fc/256) 4.800 2.400 1.200 0.600 0.300 1.200 0.600 7.200 3.600 2.400 1.800 1.200 0.600 Divisor N (Programmed in BR0CR.BR0S[3:0]) 1 2 4 8 0 5 A 1 2 3 4 6 C T0 (fc/4) 307.200 153.600 76.800 38.400 19.200 76.800 38.400 460.800 230.400 153.600 115.200 76.800 38.400 T2 (fc/16) 76.800 38.400 19.200 9.600 4.800 19.200 9.600 115.200 57.600 38.400 28.800 19.200 9.600 T8 (fc/64) 19.200 9.600 4.800 2.400 1.200 4.800 2.400 28.800 14.400 9.600 7.200 4.800 2.400 Note: This table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4 Table 14.3 UART Baud Rate Selection (When the TMRAB timer trigger output (internal TABOUT) is used and the TMRAB input clock is T1) Unit: kbps fc TA0REG 1H 2H 3H 4H 5H 6H 8H AH 10H 14H 29.4912 MHz 230.4 115.2 76.8 57.6 46.08 38.4 28.8 23.04 14.4 11.52 24.576 MHz 192 96 64 48 38.4 32 24 19.2 12 9.6 24 MHz 187.5 93.75 62.5 46.88 37.5 31.25 23.44 18.75 11.72 9.38 19.6608 MHz 153.6 76.8 51.2 38.4 30.72 25.6 19.2 15.36 9.6 7.68 16 MHz 125 62.5 41.67 31.25 25 20.83 15.63 12.5 7.81 6.25 12.288 MHz 96 48 32 24 19.2 16 12 9.6 6 4.8 When the 8-bit timer TMRAB is used to generate a serial clock, the baud rate is determined by the following equation: clock frequency selected by SYSCR0.PRCK[1:0] TABREG x 2 x 16 When the TMRAB clock source is T1 Note 1: I/O Interface mode cannot utilize the trigger output signal (internal) from the 8-bit timer TMRAB as a serial clock. Note 2: This table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4 Baud rate = TMP1962-290 2006-02-21 TMP1962C10BXBG 14.2.3 Serial Clock Generator This block generates a basic clock that controls the transmit and receive circuit. * I/O Interface mode If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the output clock from the baud rate generator is divided by two to generate the basic clock. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the external SCLK0 clock is used as the basic clock; the SC0CR.SCLKS bit determines the active clock edge. * UART mode The basic clock (SIOCLK) is selected from a clock produced by the baud rate generator, the system clock (fSYS/2), the internal output signal from the 8-bit timer TMRAB, and the external SCLK0 clock, according to the setting of the SC0MOD0.SC[1:0] field. 14.2.4 Receive Counter The receive counter is a 4-bit binary up-counter used in UART mode. This counter is clocked by SIOCLK. The receiver utilizes 16 clocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). The value of a bit is determined by voting logic which takes the value of the majority of three samples. 14.2.5 Receive Controller * I/O Interface mode If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the receive controller samples the RXD0 input at the rising edge of the shift clock driven out from the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the receive controller samples the RXD0 input at either the rising or falling edge of the SCLK0 clock, as programmed in the SC0CR.SCLKS bit. * UART mode The receive controller contains the start bit detection logic. Once a valid start bit is detected, the receive controller begins sampling the incoming data streams. 14.2.6 Receive Buffer The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit by bit into Receive Buffer 1. When a whole frame is loaded into Receive Buffer 1, it is transferred to Receive Buffer 2 (SC0BUF), and a receive-done interrupt (INTRX0) is generated. At this time, the Receive Buffer Full flag (SC0MOD2.RBFLL) is set to 1, indicating that Receive Buffer 2 contains valid data. The CPU reads a frame from Receive Buffer 2 (SC0BUF), causing the Receive Buffer Full flag (SC0MOD2.RBFLL) to be cleared to 0. Receive Buffer 1 can accept a new frame through the RXD0 pin before the CPU picks up the previous frame in Receive Buffer 2. TMP1962-291 2006-02-21 TMP1962C10BXBG If the SCLK0 pin is configured as an output in I/O Interface mode, Receive Buffer 2 (SC0BUF) can be enabled or disabled by programming the WBUF bit in the SC0MOD2. Disabling Receive Buffer 2 (double-buffering) enables handshaking during data transfer; the SIO0 stops outputting the SCLK0 clock every time a single frame has transmitted. In this case, the CPU reads a frame from Receive Buffer 1, causing the output of the SCLK0 clock to be restarted. If Receive Buffer 2 (double-buffering) is enabled, a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. Once a next frame is received, resulting in both Receive Buffers 1 and 2 containing valid data, the SIO0 stops outputting the SCLK0 clock. When the CPU reads a frame from Receive Buffer 2, the frame stored in Receive Buffer 1 is transferred to Receive Buffer 2, causing a receive-done interrupt (INTRX0) to occur and the SIO0 to restart outputting the SCLK0 clock. Consequently, no overrun error occurs if the SCLK0 pin is configured as an output in I/O Interface mode, regardless of the setting of the SC0MOD2.WBUF bit. Note: In this mode, the OEER flag in the SC0CR has no meaning; it is read as undefined. When exiting SCLK output mode, first read the SC0CR to initialize this flag. In other operating modes, Receive Buffer 2 is always enabled to improve performance during continuous transfer. However, the CPU must read Receive Buffer 2 before Receive Buffer 1 is filled with a new frame. Otherwise, an overrun error occurs, causing the frame previously in Receive Buffer 1 to be lost. Even in that case, the contents of Receive Buffer 2 and the SC0CR.RB8 bit are preserved. The SC0CR.RB8 bit holds the parity bit for an 8-bit UART frame and the most significant bit for a 9-bit UART frame. In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address frame is received. Setting the SC0MOD0.WU bit enables the wake-up feature. The receiver generates the INTRX0 interrupt only when the SC0CR.RB8 bit is set to 1. 14.2.7 Transmit Counter The transmit counter is a 4-bit binary up-counter used in UART mode. Like the receive counter, the transmit counter is also clocked by SIOCLK. The transmitter generates a transmit clock (TXDCLK) pulse every 16 SIOCLK pulses. SIOCLK 15 TXDCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 Figure 14.3 Transmit Clock Generation 14.2.8 Transmit Controller * I/O Interface mode If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the transmit controller shifts out each bit in the transmit buffer to the TXD0 pin at the rising edge of the shift clock driven out on the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the transmit controller shifts out each bit in the transmit buffer to the TXD0 pin at either the rising or falling edge of the SCLK0 input, as programmed in the SC0CR.SCLKS bit. TMP1962-292 2006-02-21 TMP1962C10BXBG * UART mode Once the CPU loads a frame into the transmit buffer, the transmit controller begins transmission at the next rising edge of TXDCLK, producing a transmit shift clock (TXDSFT). Handshaking The SIO0 has the clear-to-send (CTS) pin. If the CTS operation is enabled, the CTS input must be low in order for the frame to be transmitted. This feature can be used for flow control to prevent overrun in the receiver. The SC0MOD.CTSE bit enables and disables the CTS operation. If the CTS pin goes high in the middle of a transmission, the transmit controller stops transmission upon completion of the current frame until CTS again goes low. If so enabled, the transmit controller generates the INTTX0 interrupt to notify the CPU that the transmit buffer is empty. After the CPU loads the next frame into the transmit buffer, the transmit controller remains in idle state until it detects CTS going low. Although the SIO0 does not have an RTS pin, any general-purpose port pin can serve as the RTS pin. The receiving device uses the RTS output to control the CTS input of the transmitting device. Once the receiving device has received a frame, RTS should be set to high in the receive-done interrupt handler to temporarily stop the transmitting device from sending the next frame. This way, the user can easily implement a two-way handshake protocol. TMP1962 TMP1962 TXD CTS RXD RTS (Any port) Transmitting Device Receiving Device Figure 14.4 Handshaking Signals Write to the Transmit Buffer CTS No transmission takes place during (2) this period. (1) 13 SIOCLK 14 15 16 1 2 3 14 15 16 1 2 3 TXDCLK TXD start bit bit 0 Note: (1) When CTS goes high in the middle of transmission, the transmitter stops transmission after the current frame has been sent. (2) The transmitter starts transmission at the first falling edge of the TXDCLK clock after the CTS signal goes low. Figure 14.5 Clear-To-Send ( CTS ) Signal Timing TMP1962-293 2006-02-21 TMP1962C10BXBG 14.2.9 Transmit Buffer The transmit buffer is double-buffered. Double-buffering can be enabled or disabled by programming the WBUF bit in the SC0MOD2. If double-buffering is enabled, a frame is first written to Transmit Buffer 2 (SC0BUF) and then transferred to Transmit Buffer 1 (shift register), causing the INTTX interrupt to occur and the Transfer Buffer Empty flag (SC0MOD2.TBEMP) to be set. This flag indicates that Transfer Buffer 2 is empty and a next transmit frame can be written. Writing a next frame to Transmit Buffer 2 clears the TBEMP flag. When the SCLK0 pin is configured as an input in I/O Interface mode, an underrun error occurs upon the completion of transmitting a frame from Transmit Buffer 1, if a next frame is not written to Transfer Buffer 2 before the clock pulse for the next frame is input. An underrun error is indicated by the parity/underrun flag (PERR) in the SC0CR. When the SCLK0 pin is configured as an output in I/O Interface mode, the SIO0 stops outputting the SCLK0 clock after transmitting a frame which has been transferred from Transmit Buffer 2 to Transmit Buffer 1. In this mode, therefore, no underrun error occurs. Note: When the SCLK0 pin is configured as an output in I/O Interface mode, the PEER flag in the SC0CR has no meaning; it is read as undefined. When exiting SCLK output mode, first read the SC0CR to initialize this flag. If double-buffering is disabled, the CPU writes a transmit frame to Transmit Buffer 1. The INTTX interrupt is generated upon the completion of transmission. If handshaking is required, Transmit Buffer 2 must be disabled by clearing the WBUF bit in the SC0MOD2. For continuous transmission without handshaking, Transmit Buffer 2 can be enabled, by setting the WBUF bit, to improve performance. 14.2.10 Parity Controller For transmit operations, setting the SC0CR.PE bit enables parity generation in 7- and 8-bit UART modes. The SC0CR.EVEN bit selects either even or odd parity. If enabled, the parity controller automatically generates parity for the frame in the transmit buffer (SC0BUF). In 7-bit UART mode, the TB7 bit in the SC0BUF holds the parity bit. In 8-bit UART mode, the TB8 bit in the SC0MOD holds the parity bit. The parity bit is set after the frame has been transmitted. The SC0CR.PE and SC0CR.EVEN bits must be programmed prior to a write to the transmit buffer. For receive operations, the parity controller automatically computes the expected parity when a frame in Receive Buffer 1 is transferred to Receive Buffer 2 (SC0BUF). The received parity bit is compared to the SC0BUF.RB7 bit in 7-bit UART mode and to the SC0CR.RB8 bit in 8-bit UART mode. If a frame is received with incorrect parity, the SC0CR.PERR bit is set. In I/O Interface mode, the SC0CR.PERR bit indicates an underrun error rather than a parity error. TMP1962-294 2006-02-21 TMP1962C10BXBG 14.2.11 Error Flags The SIO0 has the following error flag bits that indicate the status of the received frame for improved data reception reliability. (1) Overrun error (OERR): Bit 4 of the SC0CR In UART and I/O Interface modes, an overrun error is reported with the OERR bit set to 1 if all bits of a new frame are received before the CPU reads the current frame from the receive buffer. Reading the flag causes it to be cleared. When the SCLK0 pin is configured as an output in I/O Interface mode, however, no overrun error occurs so that the OEER flag has no meaning and is read as undefined. (2) Parity error/underrun error (PERR): Bit 3 of the SC0CR In UART mode, this flag indicates whether a parity error has occurred. A parity error is reported when the parity bit attached to a received frame does not match the expected parity computed from the frame. Reading the flag causes it to be cleared. In I/O Interface mode, this flag indicates whether an underrun error has occurred, only when double-buffering (Transmit Buffer 2) is enabled (SC0MOD2.WBUF = 1) with the SCLK0 pin configured as an input. An underrun error is reported upon the completion of transmitting a frame from Transmit Buffer 1, if a next frame is not written to Transfer Buffer 2 before the clock pulse for the next frame is input. When the SCLK0 pin is configured as an output, no underrun error occurs so that the PEER flag has no meaning and is read as undefined. Reading the flag causes it to be cleared. (3) Framing error (FERR): Bit 2 of the SC0CR In UART mode, this flag indicates whether a framing error has occurred. A framing error is reported when a 0 is detected where a stop bit was expected. (The middle three of the 16 samples are used to determine the bit value.) Reading the flag causes it to be cleared. During reception, only a single stop bit is detected regardless of the setting of the SBLEN bit in Serial Mode Control Register 2 (SC0MOD2). Operating Mode UART Error Flag OERR PERR FERR OERR Overrun error flag Parity error flag Framing error flag Overrun error flag Function I/O Interface (SCLK Input) Underrun error flag (WBUF = 1) PERR Fixed to 0 (WBUF = 0) FERR Fixed to 0 Undefined Undefined Fixed to 0 I/O Interface (SCLK Output) OERR PERR FERR TMP1962-295 2006-02-21 TMP1962C10BXBG 14.2.12 Bit Transfer Sequence The DRCHG bit in Serial Mode Control Register 2 (SC0MOD2) determines whether the most significant bit (MSB) or least significant bit (LSB) is transmitted first in I/O Interface mode. The setting of the DRCHG bit cannot be modified while the SIO is transferring data. 14.2.13 Stop Bit Length Bit 4 (SBLEN) in the SC0MOD2 register determines the number of stop bits (1 or 2) used in UART mode. 14.2.14 Status Flag Bit 8 (RBFLL) in the SC0MOD2 register indicates whether Receive Buffer 2 is full (contains data) when double-buffering is enabled (SC0MOD2.WBUF = 1). It is set to 1 once a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. The RBFLL bit is cleared to 0 when the CPU or DMAC reads data from Receive Buffer 2. When WBUF = 0, the RBFLL bit has no meaning; it should not be used as a status flag. Bit 7 (TBEMP) in the SC0MOD2 register indicates whether Transmit Buffer 2 is empty when double-buffering is enabled (SC0MOD2.WBUF = 1). It is set to 1 once a transmit frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register). The TBEMP bit is cleared to 0 when the CPU or DMAC stores data in Transmit Buffer 2. When WBUF = 0, the TBEMP bit has no meaning; it should not be used as a status flag. 14.2.15 Transmit/Receive Buffer Configuration WBUF = 0 UART I/O Interface (SCLK Input) I/O Interface (SCLK Output) Transmit Receive Transmit Receive Transmit Receive Single Double Single Double Single Single WBUF = 1 Double Double Double Double Double Double TMP1962-296 2006-02-21 TMP1962C10BXBG 14.2.16 Signal Generation Timing (1) UART mode Receive operation Mode Interrupt Framing Error Parity Error Overrun Error 9 Data Bits Middle of the first stop bit Middle of the stop bit 8 Data Bits with Parity Middle of the first stop bit Middle of the stop bit Middle of the last bit (i.e., parity bit) Middle of the stop bit 8 Data Bits with No Parity, 7 Data Bits with Parity, 7 Data Bits with No Parity Middle of the first stop bit Middle of the stop bit Middle of the last bit (i.e., parity bit) Middle of the stop bit Middle of the stop bit Transmit operation Mode Interrupt (WBUF = 0) 9 Data Bits Immediately before the stop bit is shifted out Immediately after the frame is transferred to Transmit Buffer 1 (i.e., immediately before the stop bit is shifted out) 8 Data Bits with Parity Immediately before the stop bit is shifted out Immediately after the frame is transferred to Transmit Buffer 1 (i.e., immediately before the stop bit is shifted out) 8 Data Bits with No Parity, 7 Data Bits with Parity, 7 Data Bits with No Parity Immediately before the stop bit is shifted out Immediately after the frame is transferred to Transmit Buffer 1 (i.e., immediately before the stop bit is shifted out) Interrupt (WBUF = 1) (2) I/O Interface mode Receive operation Interrupt (WBUF = 0) SCLK Output Mode SCLK Input Mode Immediately after the rising edge of the last SCLK pulse Immediately after the rising or falling edge of the last SCLK pulse, as programmed Immediately after the rising edge of the last SCLK pulse (i.e., immediately after the frame is transferred to Receive Buffer 2) or immediately after the frame is read from Receive Buffer 2 Immediately after rising or falling edge of the last SCLK pulse, as programmed (i.e., immediately after the frame is transferred to Receive Buffer 2) Immediately after the rising or falling edge of the last SCLK pulse, as programmed SCLK Output Mode Interrupt WBUF = 1) SCLK Input Mode Overrun Error SCLK Input Mode Transmit operation Interrupt (WBUF = 0) SCLK Output Mode SCLK Input Mode SCLK Output Mode Interrupt (WBUF = 1) Immediately after the rising edge of the last SCLK pulse Immediately after the rising or falling edge of the last SCLK pulse, as programmed Immediately after the rising edge of the last SCLK pulse or immediately after the frame is transferred to Transmit Buffer 1 Immediately after rising or falling edge of the last SCLK pulse, as programmed or immediately after the frame is transferred to Transmit Buffer 1 Immediately after the rising or falling edge of the next SCLK pulse, as programmed SCLK Input Mode Underrun Error SCLK Input Mode Note 1: Do not modify any control register during transmit or receive operations. Note 2: Do not disable receive operations by clearing the SC0MOD0.RXE bit while any data is being received. TMP1962-297 2006-02-21 TMP1962C10BXBG 14.3 Register Description (Channel 0) 7 SC0MOD0 (0xFFFF_F261) Bit Symbol Read/Write Reset Value Function 0 Bit 8 of a transmitted character 6 CTSE 0 0: Disables CTS operation 1: Enables CTS operation 5 RXE 0 Receive control 0: Disables receiver 1: Enables receiver 4 WU R/W 0 Wake-up function 0: Disabled 1: Enabled 3 SM1 0 2 SM0 0 1 SC1 0 0 SC0 0 TB8 Serial transfer mode 00: I/O Interface mode 01: 7-Bit UART mode 10: 8-Bit UART mode 11: 9-Bit UART mode Serial clock (for UART) 00: TA6TRG (timer) 01: Baud rate generator 10: Internal fSYS/2 clock 11: External clock (SCLK0 input) Note: In I/O Interface mode, the Serial Control Register (SC0CR) is used to select the clock source. Wake-up function 9-Bit UART Mode 0 1 Interrupt on every received frame Interrupt only when RB8 = 1 Other Modes don't care Handshake ( CTS ) control 0 1 Disable (Accepts data streams at all times) Enable Note: First, ensure RXE is cleared to 0. Then, configure the mode registers (SC0MOD0, SC0MOD1 and SC0MOD2). Finally, set RXE to 1. Figure 14.6 Serial Mode Control Register 0 (SC0MOD0, for SIO0) 7 SC0MOD1 (0xFFFF_F266) Bit Symbol Read/Write Reset Value Function I2S0 R/W 0 IDLE 0: Off 1: On Synchronous 0: Halfduplex 1: Fullduplex 6 FDPX0 R/W 0 5 SIOEN R/W 0 SIO operation 0: Disable 1: Enable 4 3 2 1 0 SIOEN: Enables or disables the supply of clock pulses to the SIO module, except for registers. Note: When configuring the SC0MOD1 register, first set bit 5 (SIOEN) to 1 before programming other bits (I2SO and FDPX0). Figure 14.7 Serial Mode Control Register 1 (SC0MOD1, for SIO0) TMP1962-298 2006-02-21 TMP1962C10BXBG 7 SC0MOD2 (0xFFFF_F265) Bit Symbol Read/Write Reset Value Function 1 TBEMP 6 RBFLL 0 5 TXRUN R/W 0 4 SBLEN 0 3 DRCHG 0 2 WBUF 0 Doublebuffering 1 SWRST1 W 0 Software reset 0 SWRST0 W 0 Receive Transmit Transbuffer buffer mission-in-p empty flag empty flag rogress flag 0: Empty 0: Full 0: Stopped 1: Empty 1: Full 1: n progress Number of Bit sequence stop bits 0: 1 1: 2 0: LSB first 0: Disable 1: MSB first 1: Enable A write of 10 followed by a write of 01 SWRST[1:0]: A write of 10 followed by a write of 01 to this field resets the module, thus initializing the RXE bit in the SC0MOD0, the TBEMP, RBFLL and TXRUN bits in the SC0MOD2, the OERR, PERR and FERR bits in the SC0CR, and the internal circuits. WBUF: Enables or disables double-buffering for transmit (SCLK output or input) or receive (SCLK output) operation in I/O Interface mode or transmit operation in UART mode. For any other operation, double-buffering is always enabled. Specifies the bit transfer sequence in I/O Interface mode. In UART mode, the LSB is always transferred first. A status flag indicating whether transmit shift operation is in progress. When this bit is set to 1, transmit operation is in progress. When this bit is cleared to 0, transmit operation is completed (if TBEMP = 1) or the transmit buffer contains a next frame and is ready for transmission (if TBEMP = 0). A flag indicating whether Receive Buffer 2 is full. The RBFLL bit is set to 1 once a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. It is cleared when the CPU or DMAC reads the frame. If double-buffering is disabled, the RBFLL bit has no meaning. A flag indicating whether Transmit Buffer 2 is empty. The TBEMP bit is set to 1 once a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1. It is cleared when the CPU or DMAC writes a next frame to Transmit Buffer 2. If double-buffering is disabled, the TBEMP bit has no meaning. Specifies the number of transmit stop bits in UART mode. For receive operation, a single stop bit is used regardless of the setting of this bit. DRCHG: TXRUN: RBFLL: TBEMP: SBLEN: Note: If the module needs to be reset while it is transmitting data, two consecutive software reset sequences (i.e., 10, 01, 10, 01) must be programmed. Figure 14.8 Serial Mode Control Register 2 (SC0MOD2, for SIO0) TMP1962-299 2006-02-21 TMP1962C10BXBG 7 Bit Symbol SC0CR (0xFFFF_F262) Read/Write Reset Value Function RB8 R 6 EVEN R/W 0 5 PE 0 4 OERR 0 3 PERR 0 R (Cleared when read) 2 FERR 0 1 SCLKS R/W 0 0: SCLK0 0 IOC 0 0: Baud rate generator 1: SCLK0 input Bit 8 of a received character Parity type Parity 0: Odd 1: Even 0: Disabled 1: Error has occurred. 1: Enabled 1: SCLK0 Overrun Parity/ Underrun Framing Input clock in I/O Interface mode 0 1 Baud rate generator SCLK0 input Active edge for the SCLK0 input 0 1 Data is transmitted/received on the SCLK0 rising edge. Data is transmitted/received on the SCLK0 falling edge. Framing error flag Parity error/underrun error flag Overrun error flag These bits are cleared to 0 when read. Parity type 0 1 Odd parity Even parity Note 1: The SCLKS bit must be set to 0 for the SCLK0 output. Note 2: All error flags are cleared to 0 when read. Figure 14.9 Serial Control Register (SC0CR, for SIO0) TMP1962-300 2006-02-21 TMP1962C10BXBG 7 BR0CR (0xFFFF_F260) Bit Symbol Read/Write Reset Value Function 0 Must be written as 0. 6 BR0ADDE 0 5 BR0CK1 0 4 BR0CK0 R/W 0 3 BR0S3 0 2 BR0S2 0 1 BR0S1 0 0 BR0S0 0 00: T0 N+ (16 - K)/16 01: T2 function 10: T8 0: Disable 11: T32 1: Enable Clock divisor value N Clock source for baud rate generator 00 01 10 11 Internal clock T0 Internal clock T2 Internal clock T8 Internal clock T32 7 BR0ADD (0xFFFF_F267) Bit Symbol Read/Write Reset Value Function 6 5 4 3 BR0K3 0 2 BR0K2 R/W 0 1 BR0K1 0 0 BR0K0 0 Value of K in N + (16 - K)/16 Clock divisor value for baud rate generator BR0CR BR0ADD 0000 0001(K = 1) to 1111(K = 15) Note 1: The baud rate generator divisor cannot be set to 1 in UART mode if the N + (16 - K)/16 clock division function is enabled. In I/O Interface mode, the baud rate generator divisor can be set to 1 only when double-buffering is enabled. Note 2: To use the N + (16 - K)/16 clock division function, the value of K must be programmed in the BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 - K)/16 clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K)/16 clock division function can only be used in UART mode. In I/O Interface mode, this must be disabled by clearing BR0CR.BR0ADDE to 0. Figure 14.10 Baud Rate Generator Control Registers (BR0CR and BR0ADD, for SIO0) TMP1962-301 2006-02-21 TMP1962C10BXBG 7 TB7 SC0BUF (0xFFFF_F263) 7 RB7 6 TB6 6 RB6 5 TB5 5 RB5 4 TB4 4 RB4 3 TB3 3 RB3 2 TB2 2 RB2 1 TB1 1 RB1 0 TB0 0 RB0 (For receive) (For transmit) Figure 14.11 Serial Transmit/Receive Buffer Register (SC0BUF, for SIO0) TMP1962-302 2006-02-21 TMP1962C10BXBG 14.4 Operating Modes 14.4.1 Mode 0 (I/O Interface Mode) Mode 0 utilizes a synchronization clock (SCLK), which can be configured for either Output mode in which the SCLK clock is driven out from the TMP1962 or Input mode in which the SCLK clock is supplied externally. (1) Transmit operations SCLK Output mode When transmit double-buffering is disabled (SC0MOD2.WBUF = 0) in SCLK Output mode, each time the CPU writes a frame to the transmit buffer, the eight bits of the frame is shifted out on the TXD0 pin, and the synchronization clock is driven out from the SCLK0 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated. When transmit double-buffering is enabled (SC0MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register) once the CPU writes the frame to Transmit Buffer 2 when the SIO0 is not transmitting any data or once the last frame in Transmit Buffer 1 has been sent. At this time, the transmit buffer empty flag (SC0MOD2.TBEMP) is set to 1 and the INTTX0 is generated. If there is no data to be transferred from Transmit Buffer 2 to Transmit Buffer 1, however, SCLK0 output is stopped without generating the INTTX0 interrupt. Transmit Data Write Timing SCLK0 Output TXD0 INTTX0 Interrupt TBRUN bit 0 bit 1 bit 6 bit 7 bit 0 When WBUF = 0 (double-buffering disabled) Transmit Data Write Timing SCLK0 Output TXD0 INTTX0 Interrupt TBRUN TBEMP bit 0 bit 1 bit 6 bit 7 bit 0 When WBUF = 1 (double-buffering enabled) and Transmit Buffer 2 contains data TMP1962-303 2006-02-21 TMP1962C10BXBG Transmit Data Write Timing SCLK0 Output TXD0 INTTX0 Interrupt TBRUN TBEMP bit 0 bit 1 bit 6 bit 7 When WBUF = 1 (double-buffering enabled) but Transmit Buffer 2 does not contain data Figure 14.12 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode) SCLK Input mode When transmit double-buffering is disabled (SC0MOD2.WBUF = 0) in SCLK Input mode, the CPU must write a frame to the transmit buffer before the SCLK0 input is activated. The eight bits of a frame in the transmit buffer are shifted out on the TXD0 pin, synchronous to the programmed edge of the SCLK0 input. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated. The CPU must load the next frame into the transmit buffer by point A (shown in the figure below). When transmit double-buffering is enabled (SC0MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register) once the CPU writes the frame to Transmit Buffer 2 before the SCLK0 input is activated or once the last frame in Transmit Buffer 1 has been sent. At this time, the transmit buffer empty flag (SC0MOD2.TBEMP) is set to 1 and the INTTX0 interrupt is generated. If the SCLK0 input is activated before a frame is written to Transmit Buffer 2, however, the SIO0 assumes an underrun error and sends eight bits of dummy data (FFh) although the internal bit counter starts counting. Transmit Data Write Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) TXD0 INTTX0 Interrupt bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 A When WBUF = 0 (double-buffering disabled) TMP1962-304 2006-02-21 TMP1962C10BXBG Transmit Data Write Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) TXD0 INTTX0 Interrupt TBRUN TBEMP bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 A When WBUF = 1 (double-buffering enabled) and Transmit Buffer 2 contains data Transmit Data Write Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) TXD0 INTTX0 Interrupt TBRUN TBEMP PERR (indicating an underrun error) bit 0 bit 1 bit 5 bit 6 bit 7 A 1 1 When WBUF = 1 (double-buffering enabled) but Transmit Buffer 2 does not contain data Figure 14.13 Transmit Operation in I/O Interface Mode (SCLK0 Input Mode) TMP1962-305 2006-02-21 TMP1962C10BXBG (2) Receive operations SCLK Output mode When receive double-buffering is disabled (SC0MOD2.WBUF = 0) in SCLK Output mode, each time the CPU picks up the frame in Receive Buffer 1, the synchronization clock is driven out from the SCLK0 pin to shift the next frame into Receive Buffer 1. When a whole 8-bit frame has been loaded into Receive Buffer 1, the INTRX0 interrupt is generated. The SCLK output is initiated by setting the SC0MOD0.RXE bit to 1. When receive double-buffering is enabled (SC0MOD2.WBUF = 1), the frame received first is transferred to Receive Buffer 2 and then a next frame is received into Receive Buffer 1. Once a frame is transferred from Receive Buffer 1 to Receive Buffer 2, the receive buffer full flag (SC0MOD2.RBFLL) is set to 1 and the INTRX0 interrupt is generated. After a frame has been transferred to Receive Buffer 2, the CPU or DMAC should read it before all eight bits of a next frame are received. Otherwise, the INTRX0 interrupt is not generated and SCLK0 output is stopped. In that state, when the CPU or DMAC reads the frame from Receive Buffer 2, the next frame is transferred from Receive Buffer 1 to Receive Buffer 2, generating the INTRX0 interrupt to restart receive operation. Receive Data Read Timing SCLK0 Output RXD0 INTRX0 Interrupt bit 0 bit 1 bit 6 bit 7 bit 0 When WBUF = 0 (double-buffering disabled) Receive Data Read Timing SCLK0 Output RXD0 INTRX0 Interrupt RBFULL bit7 bit 0 bit 1 bit 6 bit 7 bit 0 When WBUF = 1 (double-buffering enabled) and Receive Buffer 2 is read Receive Data Read Timing SCLK0 Output RXD0 INTRX0 Interrupt RBFULL bit7 bit 0 bit 1 bit 6 bit 7 When WBUF = 1 (double-buffering enabled) but Receive Buffer 2 is not read Figure 14.14 Receive Operation in I/O Interface Mode (SCLK0 Output Mode) TMP1962-306 2006-02-21 TMP1962C10BXBG SCLK Input mode In SCLK Input mode, receive double-buffering is always enabled. A received frame is transferred to Receive Buffer 2 so that a next frame can be received continuously into Receive Buffer 1. The INTRX0 interrupt is generated every time a frame is transferred from Receive Buffer 1 to Receive Buffer 2. Receive Data Read Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) RXD0 INTRX0 Interrupt RBFULL bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 When Receive Buffer 2 is read Receive Data Read Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) RXD0 INTRX0 Interrupt RBFULL OERR bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 When Receive Buffer 2 is not read Figure 14.15 Receive Operation in I/O Interface Mode (SCLK0 Input Mode) Note: Regardless of whether SCLK0 is in Input mode or Output mode, the receiver must be enabled by setting the SC0MOD0.RXE bit to 1 in order to perform receive operations. TMP1962-307 2006-02-21 TMP1962C10BXBG (3) Full-duplex transmit/receive operations Setting bit 6 (FDPX0) in Serial Control Register 1 (SC0MOD1) to 1 enables full-duplex communication. SCLK Output mode When transmit/receive double-buffering is disabled (SC0MOD2.WBUF = 0) in SCLK Output mode, each time the CPU writes a frame to the transmit buffer, the synchronization clock is driven out from the SCLK0 pin to shift an 8-bit frame into Receive Buffer 1, generating the INTRX0 interrupt. At the same time, the frame written to the transmit buffer is shifted out on the TXD0 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated and SCLK0 output is stopped. When the CPU subsequently picks up the frame in the receive buffer and writes a next frame to the transmit buffer, next transmit/receive operation starts, regardless of whether the CPU first reads the receive buffer or it first writes data to the transmit buffer. When transmit/receive double-buffering is enabled (SC0MOD2.WBUF = 1), each time the CPU writes a frame to Transmit Buffer 2, the synchronization clock is driven out from the SCLK0 pin to shift an 8-bit frame into Receive Buffer 1; it is then transferred to Receive Buffer 2, generating the INTRX0 interrupt. At the same time, the frame stored in Transmit Buffer 1 is shifted out on the TXD0 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated and the next frame is transferred from Transmit Buffer 2 to Transmit Buffer 1. During the above sequence, SCLK0 output is stopped if Transmit Buffer 2 does not contain data (SC0MOD2.TBEMP = 1) or if Receive Buffer 2 still contains data (SC0MOD2.RBFLL = 1). When the CPU subsequently picks up the frame in Receive Buffer 2 and writes a next frame to Transmit Buffer 2, SCLK0 output is restarted so that next transmit/receive operation starts. TMP1962-308 2006-02-21 TMP1962C10BXBG Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 When WBUF = 0 (double-buffering disabled) Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 When WBUF = 1 (double-buffering enabled) and no error occurs Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 When WBUF = 1 (double-buffering enabled) and an error occurs Figure 14.16 Full-Duplex Transmit/Receive Operation in I/O Interface Mode (SCLK0 Output Mode) TMP1962-309 2006-02-21 TMP1962C10BXBG SCLK Input mode When transmit double-buffering is disabled (SC0MOD2.WBUF = 0) in SCLK Input mode (receive double-buffering is always enabled in this mode), the CPU must write a frame to the transmit buffer before the SCLK0 input is activated. The eight bits of a frame in the transmit buffer are shifted out on the TXD0 pin, and the eight bits of a received frame are shifted into Receive Buffer 1, synchronous to the programmed edge of the SCLK0 input. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated. When all the bits have been received, the frame is transferred from Receive Buffer 1 to Receive Buffer 2, generating the INTRX0 interrupt. The CPU must load the next frame into the transmit buffer by point A (shown in the figure below). The CPU must also pick up the frame in Receive Buffer 2 before a next frame has been received. When transmit/receive double-buffering is enabled (SC0MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 once the last frame in Transmit Buffer 1 has been sent. At this time, the INTTX0 interrupt is generated. When the 8-bit frame, received in parallel with transmission, has been shifted into Receive Buffer 1, it is transferred to Receive Buffer 2, generating the INTRX0 interrupt. When the SLCK0 is subsequently activated, the frame stored in Transmit Buffer 1 is shifted out while a next frame is received into Receive Buffer 1. If the CPU does not read the frame from Receive Buffer 2 before the last bit of a next frame is received, an overrun error occurs. If the CPU does not write a frame to Transmit Buffer 2 before the SCLK0 input is subsequently activated, an underrun error occurs. TMP1962-310 2006-02-21 TMP1962C10BXBG Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 When WBUF = 0 (double-buffering disabled) Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 When WBUF = 1 (double-buffering enabled) and no error occurs Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt PERR (Underrun Error) bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 When WBUF = 1 (double-buffering enabled) and an error occurs Figure 14.17 Full-Duplex Transmit/Receive Operation in I/O Interface Mode (SCLK0 Input Mode) TMP1962-311 2006-02-21 TMP1962C10BXBG 14.4.2 Mode 1 (7-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 01 puts the SIO0 in 7-Bit UART mode. In this mode of operation, the parity bit can be added to the transmitted frame, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity. The SBLEN bit in the SC0MOD2 specifies the number of stop bits. Example: Transmitting 7-bit UART frames with an even-parity bit start bit 0 1 2 3 4 5 6 even parity stop Goes out first (transfer rate = 2400 bps @fc = 24.576 MHz) Clocking conditions: System clock: High-speed clock gear: Prescaler clock: 76543210 PGCR PGFC SC0MOD SC0CR BR0CR IMC4LH SC0BUF High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) - - - - - - 1 - - - - - - - 1 - X0 - X0 1 0 1 X1 1 XXX0 0 0 0 1 0 1 0 1 0 - - 1 1 0 1 0 0 * * * * * * * * Configures the PG1 pin as TXD0. Selects 7-Bit UART mode. Selects even parity. Sets the transfer rate to 2400 bps. Enables the INTTX0 interrupt and sets its priority level to 4. Loads the transmit buffer with a frame. Note: X = Don't care, - = No change 14.4.3 Mode 2 (8-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 10 puts the SIO0 in 8-Bit UART mode. In this mode of operation, the parity bit can be added to the transmitted frame, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity. Example: Transmitting 8-bit UART frames with an odd-parity bit start bit 0 1 2 3 4 5 6 7 odd parity stop Goes out first (transfer rate = 9600 bps @fc = 24.576 MHz) Clocking conditions: System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x1 (fc) fperiph/4 (fperiph = fsys) TMP1962-312 2006-02-21 TMP1962C10BXBG * Settings in the main routine 76543210 PGCR PGFC SC0MOD SC0CR BR0CR IMC4LL SC0MOD - - - - - 0 - - - - - - - 1 - - - 0 0 X1 0 0 1 X0 1 XXX0 0 0 0 0 1 0 1 0 1 - - 1 1 0 1 0 0 - - 1 X- - - - Configures the PG2 pin as RXD0. Selects 8-Bit UART mode. Selects odd parity. Sets the transfer rate to 9600 bps. Enables the INTRX0 interrupt and sets its priority level to 4. Enables reception. * Example of interrupt routine processing INTCLR Reg. if Reg. Reg. XX0 1 0 0 0 0 SC0CR AND 0x1C 0 then Error SC0BUF Clears the interrupt request. Checks for errors. Reads received data. End of interrupt processing Note: X = Don't care, - = No change TMP1962-313 2006-02-21 TMP1962C10BXBG 14.4.4 Mode 3 (9-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 11 puts the SIO0 in 9-Bit UART mode. In this mode, a parity bit cannot be used; thus, parity should be disabled by clearing the SC0CR.PE bit to 0. For transmit operations, the most-significant bit (9th bit) is stored in bit 7 (TB8) in the SC0MOD0. For receive operations, the most-significant bit is stored in bit 7 (RB8) in the SC0CR. Reads and writes of the transmit/receive frame must be done with the most-significant bit first, followed by the SC0BUF. The SBLEN bit in the SC0MOD2 specifies the number of stop bits. Wake-up Feature In 9-Bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address frame is received. Setting the SC0MOD0.WU bit enables the wake-up feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the receiver generates the INTRX0 interrupt. TXD RXD TXD RXD TXD RXD TXD RXD Master Slave 1 Slave 2 Slave 3 Note: The slave controller's TXD pin must be configured as an open-drain output by programming the ODE register. Figure 14.18 Serial Link Using the Wake-Up Function TMP1962-314 2006-02-21 TMP1962C10BXBG Protocol (1) Put all the master and slave controllers in 9-Bit UART mode. (2) Enables the receiver in each slave controller by setting the SC0MOD0.WU bit to 1. (3) The master controller transmits an 8-bit address frame (i.e, select code) that identifies a slave controller. The address character has the most-significant bit (bit 8) set to 1. start bit 0 1 2 3 4 5 6 7 8 "1" stop Slave controller select code (4) Each slave controller compares the received address to its station address and clears the WU bit if they match. (5) The master controller transmits a block of data to the selected slave controller (with SC0MOD0.WU bit cleared). Data frames have the most-significant bit (bit 8) cleared to 0. start bit 0 1 2 3 Data 4 5 6 7 bit 8 "0" stop (6) Slave controllers not addressed continue to monitor the data stream, but discard any frames with the most-significant bit (RB8) cleared, and thus do not generate receive-done interrupts (INTRX0). The addressed slave controller with its WU bit cleared can transmit data to the master controller to notify that it has successfully received the message. Example: Connecting a master station with two slave stations through a serial link using the fSYS/2 clock as a serial clock TXD RXD TXD RXD TXD RXD Master Slave 1 Select Code 00000001 Slave 2 Select Code 00001010 TMP1962-315 2006-02-21 TMP1962C10BXBG * Master controller settings Main routine PGCR PGFC IMC4LL IMC4LH SC0MOD0 SC0BUF - - - - - 0 1 - - - - - - 1 1 - - - 1 1 0 1 0 1 - - 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 Configures the PG1 pin as TXD0 and the PG2 pin as RXD0. Enables INTRX0 and sets its interrupt level to 5. Enables INTTX0 and sets its interrupt level to 4. Selects 9-Bit UART mode and selects fSYS/2 as a serial clock. Loads the select code for slave 1. Interrupt routine (INTTX0) INTCLR SC0MOD0 SC0BUF XX0 1 0 0 0 1 0 - - - - - - - * * * * * * * * Clears the interrupt request. Clears the TB8 bit to 0. Loads the transmit data. End of interrupt processing * Slave controller settings Main routine PDCR PDFC PGODE IMC4LL IMC4LH SC0MOD0 - - - - - 0 1 - - - - - - 1 1 - - - - - - - 1 - - - 1 1 0 1 1 0 - - 1 1 0 1 0 1 0 0 1 1 1 1 1 0 Configures the PD0 pin as TXD (open-drain output) and the PD1 pin as RXD. Enables INTTX0 and INTRX0. Selects 9-Bit UART mode, selects fSYS/2 as a serial clock and sets the WU bit to 1. Interrupt routine (INTRX0) INTCLR Reg. if Reg. Then SC0MOD0 XX0 1 0 0 0 0 SC0BUF = Select code Clears the interrupt request. - - - 0 - - - - Clears the WU bit to 0. TMP1962-316 2006-02-21 TMP1962C10BXBG 15. Serial Bus Interface (SBI) The TMP1962 contains a Serial Bus Interface (SBI) channel, which has the following two operating modes: * * I2C Bus mode (with multi-master capability) Clock-Synchronous 8-Bit SIO mode In I2C Bus mode, the SBI is connected to external devices via two pins, PF0 (SDA) and PF1 (SCL). In Clock-Synchronous 8-Bit SIO mode, the SBI is connected to external devices via three pins, PF2 (SCK), PF2 (SO) and PF1 (SI). The following table shows the programming required to put the SBI in each operating mode. PFODE I C Bus Mode Clock-Synchronous 8-Bit SIO Mode X: Don't care 2 PFCR PFFC X11 101 (clock output) 001 (clock input) 011 111 11 XX 15.1 Block Diagram Figure 15.1 shows a block diagram of the SBI. INTS Interrupt Request SCL SCK SIO Clock Control PF2 (SCK) Input/ Output Control SIO Data Control SO SI fsys/4 Divider Transfer Control Logic PF0 (SO/SDA) Noise Canceller I C Bus Clock Synchro-ni zation/ Control 2 Shift Register I C Bus Data Control 2 PE1 (SI/SCL) Noise Canceller SDA SBICR2/ SBISR SBI Control Register 2/ SBI Status Register 2 I2CAR I C Bus 0 Address Register SBIDBR SBI Data Buffer Register SBICR0,1 SBIBR0, 1 SBI Control SBI Baud Rate Registers 0 and 1 Registers 0 and 1 Figure 15.1 SBI Block Diagram TMP1962-317 2006-02-21 TMP1962C10BXBG 15.2 Registers A listing of the registers used to control the SBI follows: * * * * * * * * Serial Bus Interface Control Register 0 (SBICR0) Serial Bus Interface Control Register 1 (SBICR1) Serial Bus Interface Control Register 2 (SBICR2) Serial Bus Interface Data Buffer Register (SBIDBR) I2C Bus Address Register (I2CAR) Serial Bus Interface Status Register (SBISR) Serial Bus Interface Baud Rate Register 0 (SBIBR0) Serial Bus Interface Baud Rate Register 1 (SBIBR1) The functions of these registers vary, depending on the mode in which the SBI is operating. For a detailed description of the registers, refer to Section 15.4, "Description of the Registers Used in I2C Bus Mode," and Section 15.7, "Description of the Registers Used in Clock-Synchronous 8-Bit SIO Mode." 15.3 I2C Bus Mode Data Formats Figure 15.2 shows the serial bus interface data formats used in I2C Bus mode. (a) Addressing format 8 bits S Slave address Once 1 RA /C WK 1 to 8 bits Data 1 A C K Repeated 1 to 8 bits Data 1 A CP K (b) Addressing format (with repeated START condition) 8 bits S Slave address Once 1 RA /C WK 1 to 8 bits Data Repeated 1 A CS K 8 bits Slave address Once 1 RA /C WK 1 to 8 bits Data Repeated 1 A CP K (c) Free data format (master-transmitter to slave-receiver) 8 bits S Data Once 1 A C K 1 to 8 bits Data 1 A C K Repeated 1 to 8 bits Data 1 A CP K Note: S = START condition R/ W = Direction bit ACK = Acknowledge bit P = STOP condition Figure 15.2 I2C-Bus Mode Data Formats TMP1962-318 2006-02-21 TMP1962C10BXBG 15.4 Description of the Registers Used in I2C Bus Mode This section provides a summary of the registers which control I2C bus operation and provide I2C bus status information for bus access/monitoring. Serial Bus Interface Control Register 0 7 SBICR0 (0xFFFF_F254) Bit Symbol Read/Write Reset Value Function SBIEN R/W 0 SBI operation 0: Disable 1: Enable 6 5 4 3 2 1 0 SBIEN: Enables or disables the operation of the SBI. If the SBI is disabled, no clock pulses are supplied to the SBI registers other than the SBICR0, so that power consumption in the system can be reduced (only the SBICR0 can be read or written). To use the SBI, set the SBIEN bit to 1 before configuring other registers of the SBI. Once the SBI operates, all settings in its registers are held if it is disabled. Note: Bits 0 to 6 of the SBICR0 are read as 0. Figure 15.3 I2C Bus Mode Registers TMP1962-319 2006-02-21 TMP1962C10BXBG Serial Bus Interface Control Register 1 7 SBICR1 (0xFFFF_F253) Bit Symbol Read/Write Reset Value Function 0 BC2 6 BC1 W 0 5 BC0 4 ACK R/W 3 2 SCK2 W 0 1 SCK1 0 SCK0/ SWRMON R/W 0 1 0 0 Number of bits per transfer (Note 1) ACK clock pulse 0: No ACK 1: ACK Internal SCL output clock frequency (Note 2) / Software reset monitor On writes: SCK[2:0] = Internal SCL output clock frequency 000 n=4 506 kHz 001 n=5 010 n=6 011 n=7 100 n=8 101 n=9 110 n=10 111 281 kHz 149 kHz 77 kHz 39 kHz 20 kHz 10 kHz reserved Frequency = Clock gear System clock: fsys (= 40.5 MHz) : fc/1 fsys/4 2 +4 n [ Hz ] On reads: SWRMON = Software reset monitor 0 1 Software reset operation is in progress. Software reset operation is not in progress. Number of bits per transfer ACK = 0 Number of clock cycles ACK = 1 Number of clock cycles Data length 8 1 2 3 4 5 6 7 Data length 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 Note 1: Clear the BC[2:0] field to 000 before switching the operating mode to Clock-Synchronous 8-Bit SIO mode. Note 2: For details on the SCL bus clock frequency, refer to Section 15.5.3, "Serial Clock." Figure 15.4 I2C Bus Mode Registers TMP1962-320 2006-02-21 TMP1962C10BXBG Serial Bus Interface Control Register 2 7 SBICR2 (0xFFFF_F250) Bit Symbol Read/Write Reset Value Function 0 Master/ slave 0: Slave 1: Master 0 Transmit/ receive 0: Receive 1: Transmit 6 TRX W 5 BB 0 START/ STOP generation 0: STOP condition 1: START condition 4 PIN 1 INTS interrupt clear 0: 1: Interrupt clear 3 SBIM1 0 Operating mode (Note 2) 00: Port mode 01: SIO mode W (Note 1) 2 SBIM0 0 1 SWRST1 0 Software reset W (Note 1) 0 SWRST0 0 MST A write of 10 followed by a write of 01 10: I C Bus mode 11: Reserved 2 Operating mode (Note 2) 00 Port mode (serial bus interface output disabled) 01 Clock-Synchronous 8-Bit SIO mode 10 I C Bus mode 11 Reserved 2 Note 1: Reading this register causes it to function as a status register (SBISR). Note 2: Ensure that the bus is free before switching the operating mode to Port mode. Ensure that the port is at logic 2 high before switching from Port mode to I C Bus or SIO mode. Figure 15.5 I2C Bus Mode Registers Table 15.1 Base Clock Resolutions @fsys = 40.5 MHz Clock Gear Value GEAR[1:0] 00 (fc) Base Clock Resolution fsys/2 (0.1 s) 2 01 (fc/2) fsys/2 (0.2 s) 3 10 (fc/4) fsys/2 (0.4 s) 4 11 (fc/8) fsys/2 (0.8 s) 5 TMP1962-321 2006-02-21 TMP1962C10BXBG Serial Bus Interface Status Register 7 Bit Symbol SBISR (0xFFFF_F250) Read/Write Reset Value Function MST 0 Master/ slave 0: Slave 1: Master 6 TRX 0 Transmit/ receive 0: Receive 1: Transmit 2 5 BB 0 I C bus status 0: Free 1: Busy 4 PIN R 1 INTS interrupt status 3 AL 0 Arbitration lost 0: - 2 AAS 0 Addressed as slave 0: 1: Detected 0: - 1 AD0 0 General call 1: Detected 0 LRB 0 Last received bit 0: 0 1: 1 0: The 1: Detected interrupt is asserted. 1: The interrupt is not asserted Last received bit 0 1 The last bit received was 0. The last bit received was 1. Addressed as slave 0 1 The address on the bus matches the slave address or general-call address Arbitration lost 0 1 Arbitration was lost to another master. Note: Writing to this register causes it to function as a control register (SBICR2). Figure 15.6 I2C Bus Mode Registers TMP1962-322 2006-02-21 TMP1962C10BXBG Serial Bus Interface Baud Rate Register 0 7 Bit Symbol SBIBR0 (0xFFFF_F257) Read/Write Reset Value Function 6 I2SBI0 R/W 0 IDLE 0: Off 1: On 5 4 3 2 1 0 W 0 Must be written as 0. SBI on/off in IDLE2 mode 0 1 Off On Serial Bus Interface Baud Rate Register 1 7 SBIBR1 (0xFFFF_F256) Bit Symbol Read/Write Reset Value Function P4EN R/W 0 Internal clock 0: Off 1: On Controls the internal baud rate generator 0 1 Off On 6 5 4 3 2 1 0 Serial Bus Interface Data Buffer Register 7 SBIDBR (0xFFFF_F252) Bit Symbol Read/Write Reset Value DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (receive) / W (transmit) Undefined Note: In Transmitter mode, data must be written to this register, with bit 7 being the most-significant bit (MSB). I2C Bus Address Register 7 I2CAR (0xFFFF_F251) Bit Symbol Read/Write Reset Value Function 0 0 0 0 SA6 6 SA5 5 SA4 4 SA3 W 3 SA2 0 2 2 SA1 0 1 SA0 0 0 ALS 0 Address Recogniti on mode When the SBI is addressed as a slave, this field specifies a 7-bit I C-bus address to which the SBI responds. Address Recognition mode 0 1 Recognizes the slave address. Does not recognize the slave address. Figure 15.7 I2C Bus Mode Registers TMP1962-323 2006-02-21 TMP1962C10BXBG 15.5 I2C Bus Mode Configuration 15.5.1 Acknowledgment Mode Setting the SBICR1.ACK bit selects Acknowledge mode. When operating as a master, the SBI generates a clock pulse for acknowledge automatically after each data. As a transmitter, the SBI releases the SDA line during this acknowledge cycle so that the receiver of the data transfer can drive the SDA line low to acknowledge receipt of the data. As a receiver, the SBI pulls the SDA line low during the acknowledge cycle after each data has been received. Clearing the SBICR1.ACK bit selects Non-Acknowledge mode. When operating as a master, the SBI does not generate acknowledge clock pulses. 15.5.2 Number of Bits Per Transfer The SBICR1.BC[2:0] field specifies the number of bits of the next data item to be transmitted or received. After a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction (R/W) bit to be transferred in a packet of eight bits. At other times, the SBICR1.BC[2:0] field keeps a previously programmed value. 15.5.3 Serial Clock (1) Clock source The SBICR1.SCK[2:0] field controls the maximum frequency of the serial clock driven out on the SCL pin in Master mode, as illustrated below. tHIGH tLOW 1/fscl SBI0CR1 tLOW = 2 /(fsys/4) tHIGH = 2 /(fsys/4) + 4/(fsys/4) fscl = 1/(tLow + tHIGH) fsys/4 = n 2 +4 n-1 n-1 n 4 5 6 7 8 9 10 000 001 010 011 100 101 110 Figure 15.8 Clock Source TMP1962-324 2006-02-21 TMP1962C10BXBG (2) Clock synchronization Clock synchronization is performed using the wired-AND connection of all I2C-bus components to the bus. If two or more masters try to transfer messages on the I2C bus, the first to pull its clock line low wins the arbitration, overriding other masters producing a high on their clock lines. Clock signals of two or more devices on the I2C-bus are synchronized to ensure correct data transfers. Figure 15.9 shows a depiction of the clock synchronization mechanism for the I2C bus with two masters. Wait State Start counting HIGH period Internal SCL Level (Master A) Internal SCL Level (Master B) Counter reset SCL Bus Line a b c Figure 15.9 Clock Synchronization Example At point a, Master A pulls its internal SCL level low, bringing the SCL bus line low. The high-to-low transition on the SCL bus line causes Master B to reset its high-level counter and pull its internal SCL level low. Master A completes its low period at point b. However, the low-to-high transition on its internal SCL level does not change the state of the SCL bus line if Master B's internal SCL level is still within its low period. Therefore, Master A enters a high wait state, where it does not start counting off its high period. When Master B has counted off its low period at point c, its internal SCL level goes high, releasing the SCL bus line (high). There will then be no difference between the internal SCL levels and the state of the SCL bus line, and both Master A and Master B start counting off their high periods. This way, a synchronized SCL clock is generated with its high period determined by the master with the shortest clock high period and its low period determined by the one with the longest clock low period. 15.5.4 Slave Addressing and Address Recognition Mode When the SBI is configured to operate as a slave, the SA[6:0] field in the I2CAR must be loaded with the 7-bit I2C-bus address to which the SBI is to respond. The ALS bit must be cleared for the SBI to recognize the incoming slave address. 15.5.5 Configuring the SBI as a Master or a Slave Setting the SBICR2.MST bit configures the SBI as a master, and clearing it configures the SBI as a slave. This bit is cleared by hardware when a STOP condition has been detected and when arbitration for the I2C bus has been lost. TMP1962-325 2006-02-21 TMP1962C10BXBG 15.5.6 Configuring the SBI as a Transmitter or a Receiver The SBICR2.TRX bit is set or cleared by hardware to configure the SBI as a transmitter or a receiver. As a slave, the SBI is put in either Slave-Receiver or Slave-Transmitter mode, depending on the value of the data direction (R/W) bit transmitted by the master. When the SBI is addressed as a slave, the TRX bit reflects the value of the R/W bit. The TRX bit is set or cleared on the following occasions: * * * when transferring data using addressing format when the received slave address matches the value in the I2CCR when a general-call address is received; i.e., the eight bits following the START condition are all zeros. As a master, the SBI is put in either Master-Transmitter or a Master-Receiver mode upon reception of an acknowledge from an addressed slave. The TRX bit changes to the opposite value of the R/W bit sent by the SBI. If the SBI does not receive an acknowledge from a slave, the TRX bit retains the previous value. The TRX bit is cleared by hardware when a STOP condition has been detected and when arbitration for the I2C bus has been lost. 15.5.7 Generating START and STOP Conditions When the SBISR.BB bit is cleared, the bus is free. At this time, writing 1s to the MST, TRX, BB and PIN bits in the SBICR2 causes the SBI to generate a START condition on the bus and shift out 8-bit I2C-bus data. Before generating a START condition, the ACK bit must be set to 1. SCL Line 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 SDA Line START Condition Slave Address and Direction Bit Acknowledge Signal Figure 15.10 Generating a START Condition and a Slave Address When the SBISR.BB bit is set, the bus is busy. When SBISR.BB = 1, writing 1s to the MST, TRX and PIN bits and a 0 to the BB bit causes the SBI to start a sequence for generating a STOP condition on the bus to abort the transfer. The MST, TRX, BB and PIN bits should not be altered until a STOP condition appears on the bus. SCL Line SDA Line STOP Condition Figure 15.11 Generating a STOP Condition The BB bit can be read to determine if the I2C bus is in use. The BB bit is set when a START condition is detected and cleared when a STOP condition is detected. TMP1962-326 2006-02-21 TMP1962C10BXBG 15.5.8 Asserting and Deasserting Interrupt Requests When an SBI interrupt (INTS) is generated, the PIN bit in the SBICR2 is cleared to 0. While the PIN bit is 0, the SBI pulls the SCL line low. After transmission or reception of one data word on the I2C bus, the PIN bit is automatically cleared. In Transmitter mode, the PIN bit is subsequently set to 1 each time the SBIDBR is written. In Receiver mode, the PIN bit is set to 1 each time the SBIDBR is read. It takes a period of tLOW for the SCL line to be released after the PIN bit is set. In Address Recognition mode (ALS = 0), the PIN bit is cleared when the SBI is addressed as a slave and the received slave address matches the value in the I2CCR or is all 0s (i.e., a general call). A write of 1 by software sets the PIN bit, but a write of 0 has no effect on this bit. 15.5.9 SBI Operating Modes The SBIM[1:0] field in the SBICR2 is used to select an operating mode of the SBI. To configure the SBI for I2C Bus mode, set the SBIM[1:0] field to 10. A switch to Port mode should only be attempted when the bus is free. 15.5.10 Lost-Arbitration Detection Monitor The I2C bus is a multi-master bus and has an arbitration procedure to ensure correct data transfers. A master may start a transfer only if the bus is free. A master that attempts to generate a START condition while the bus is busy loses bus arbitration, with no START condition occurring on the SDA and SCL lines. The I2C-bus arbitration takes place on the SDA line. Figure 15.12 shows the arbitration procedure for two masters. Up until point a, the internal data levels of Master A and Master B are the same. At point a Master B's internal data level makes a low-to-high transition while Master A's internal data level remains at logic low. However, the SDA bus line is held low because it is the wired-AND of the two data outputs. When the SCL bus clock goes high at point b, the addressed slave device reads the data transmitted by Master A (i.e., winning master). Master B loses arbitration and switches off its data output stage, releasing its SDA line (high), so that it does not affect the data transfer initiated by the winning master. In case two competing masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. SCL Bus Line Internal SDA Level (Master A) Internal SDA Level (Master B) SDA Bus Line a b Master B loses arbitration and connects a high output level to the bus. Figure 15.12 Arbitration Procedure of Two Masters TMP1962-327 2006-02-21 TMP1962C10BXBG A master compares its internal data level to the actual level on the SDA line at the rising edge of the SCL clock. The master loses arbitration if there is a difference between these two values. The losing master sets the AL bit in the SBISR to 1, which causes the MST and TRX bits in the same register to be cleared. That is, the losing master switches to Slave-Receiver mode. The AL bit is subsequently cleared when data is written to or read from the SBIDBR and when the SBICR2 is programmed with new parameters. Internal SCL Level Internal SDA Level Internal SCL Level Internal SDA Level Master A D7A' D6A' D5A' D4A' Clock output stops here Master B 1 D7B 2 D6B 3 4 Internal SDA level is held high because Master B has lost arbitration. Figure 15.13 Master B Loses Arbitration (D7A = D7B, D6A = D6B) 15.5.11 Slave Address Match Monitor When acting as a slave-receiver, the ALS bit in the I2CCR determines whether the SBI recognizes the incoming slave address or not. In Address Recognition mode (i.e., ALS = 0), the AAS bit in the SBISR is set when an incoming address over the I2C bus matches the value in the I2CCR or when the general-call address has been received. When ALS = 1, the AAS bit is set when the first data word has been received. The AAS bit is cleared each time the SBIDBR is read or written. 15.5.12 General-Call Detection Monitor When acting as a slave-receiver, the AD0 bit in the SBISR is set when a general-call address has been received. The general-call address is detected when the eight bits following a START condition are all zeros. The AD0 bit is cleared when a START or STOP condition is detected on the bus. 15.5.13 Last Received Bit Monitor The LRB bit in the SBISR holds the value of the last bit received over the SDA line at the rising edge of the SCL clock. In Acknowledge mode, reading this bit immediately after generation of the INTS2 interrupt returns the value of the ACK signal. TMP1962-328 2006-02-21 TMP1962C10BXBG 15.5.14 Software Reset The SBI provides a software reset, which permits recovery from system lockups caused by external noise. A software reset is performed by a write of 10 followed by a write of 01 to the SWRST[1:0] field in the SBICR2. After a software reset, all control and status register bits are initialized to their reset values. Upon resetting the SBI, the SWRST[1:0] field is automatically cleared to 00. Note: A software reset causes the SBI operating mode to switch from I C Bus mode to Clock-Synchronous mode. 2 15.5.15 Serial Bus Interface Data Buffer Register (SBIDBR) The SBIDBR is a data buffer interfacing to the I2C bus. All read and write operations to/from the I2C bus are done via this register. When the SBI is acting as a master, loading this register with a slave address and a data direction bit causes a START condition to be generated. 15.5.16 I2C Bus Address Register (I2CAR) When the SBI is configured as a slave, the SA[6:0] field in the I2CAR must be loaded with the 7-bit I C-bus address to which the SBI is to respond. If the ALS bit in the I2CAR is cleared, the SBI recognizes a slave address transmitted by the master device, interpreting incoming frame structures as per addressing format. If the ALS bit is set, the SBI does not recognize a slave address and interprets all frame structures as per free data format. 2 15.5.17 Baud Rate Register (SBIBR1) Before the I2C bus can be used, the P4EN bit in the SBIBR1 must be set to enable the SBI internal baud rate generation logic. 15.5.18 IDLE Setting Register (SBIBR0) The I2SBI bit in the SBIBR0 determines whether the SBI is shut down or not when the TMP1962 is put in IDLE standby mode. This register must be programmed before executing an instruction for entering a standby mode.. TMP1962-329 2006-02-21 TMP1962C10BXBG 15.6 Programming Sequences in I2C Bus Mode 15.6.1 SBI Initialization First, program the P4EN bit in the SBIBR1, and the ACK and SCK[2:0] bits in the SBICR1. Set the SBIBR1.P4EN bit to 1 to enable the internal baud rate generation logic. Write 0s to bits 7-5 and bit 3 in the SBICR1. Next, program the I2CAR. The SA[6:0] field in the I2CAR defines the chip's slave address, and the ALS bit (bit 0) selects an address recognition mode. (The ALS bit must be cleared when using the addressing format.) Next, program the SBICR2 to initially configure the SBI in Slave-Receiver mode; i.e., clear the MST, TRX and BB bits to 0, set the PIN bit to 1 and set the SBIM[1:0] field to 10. Write 00 to the SWRST[1:0] field. 76543210 SBIBR1 SBICR1 I2CAR SBICR2 1 0 0 0 0 0 0 0 0 0 0 X0 XXX XXXXXXXX 0 0 0 1 1 0 0 0 Enables internal baud rate generator. Disables generation of ACK and selects SCL clock frequency. Loads a slave address and selects address recognition mode. Configures the SBI in Slave-Receiver mode. Note: X = Don't care 15.6.2 Generating a START Condition and a Slave Address (1) Master mode In Master mode, the following steps are required to generate a START condition and a slave address on the I2C-bus. First, ensure that the bus is free (i.e., SBICR2.BB = 0). Next, set the ACK bit in the SBICR1 to enable generation of acknowledge clock pulses. Then, load the SBIDBR with a slave address and a data direction bit to be transmitted via the I2C bus. When BB = 0, writing 1s to the MST, TRX, BB and PIN bits in the SBICR2 causes a START condition to be generated on the bus. Following a START condition, the SBI generates SCL clock pulses nine times: the SBI shifts out the contents of the SBIDBR with the first eight SCL clocks, and releases the SDA line during the last (i.e., ninth) SCL clock to receive an acknowledgement signal from the addressed slave. The INTS interrupt request is generated on the falling edge of the ninth SCL clock pulse, and the PIN bit in the SBICR2 is cleared to 0. In Master mode, the SBI holds the SCL line low while the PIN bit is 0. Upon interrupt, the TRX bit either remains set or is cleared according to the value of the transmitted direction bit, provided an acknowledgement signal has been returned from the slave. TMP1962-330 2006-02-21 TMP1962C10BXBG Settings in main routine 76543210 Reg. Reg. if Reg. Then SBICR1 SBIDR1 SBICR2 XXX1 0 XXX XXXXXXXX 1 1 1 1 1 0 0 0 Selects Acknowledgement mode. Loads the slave address and a data direction bit. Generates a START condition. SBISR Reg. e 0x20 0x00 Ensures that the bus is free. INTS interrupt routine INTCLR 0X14 Interrupt processing End of interrupt Clears the interrupt request. (2) Slave mode In Slave mode, the following steps are required to receive a START condition and a slave address via the I2C bus. Upon detection of a START condition, the SBI clocks in a 7-bit slave address and a data direction bit transmitted by the master during the first eight SCL clock pulses. If the received slave address matches its own address in the I2CAR or is equal to the general-call address (00H), the SBI pulls the SDA line low during the last (i.e., ninth) SCL clock for acknowledgement. The INTS interrupt request is generated on the falling edge of the ninth SCL clock pulse, and the PIN bit in the SBICR2 is cleared to 0. In Slave mode, the SBI holds the SCL line low while the PIN bit is 0. Note: The user can only use a DMA transfer: * * when there is only one master and only one slave on the I C bus; and continuous transmission or reception is possible. 2 SCL 1 A6 START Condition 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 9 ACK Acknowledgme nt from slave SDA R/ W Slave Address + Direction Bit Figure 15.14 Generation of a START Condition and a Slave Address TMP1962-331 2006-02-21 TMP1962C10BXBG 15.6.3 Transferring a Data Word Each time a data word has been transmitted or received, the INTS interrupt is generated. It is the responsibility of the INTS interrupt service routine to test the MST bit in the SBICR2 to determine whether the SBI is in Master or Slave mode. (1) Master mode (SBICR2.MST = 1) If the MST bit in the SBICR2 is set, then test the TRX bit in the same register to determine whether the SBI is in Master-Transmitter or Master-Receiver mode. Master-Transmitter mode (SBICR2.TRX = 1) Test the LRB bit in the SBISR. If the LRB bit is set, that means the slave-receiver requires no further data to be sent from the master-transmitter. The master-transmitter must then generate a STOP condition as described later to stop transmission. If the LRB bit is cleared, that means the slave-receiver requires further data. If the number of bits per transfer is 8, then write the transmit data into the SBIDBR. When using other data length, program the BC[2:0] and ACK bits in the SBICR1, and then write the transmit data into the SBIDBR. When the SBIDBR is loaded, the PIN bit in the SBISR is set to 1, and the transmit data is shifted out from the SDA0 pin, clocked by the SCL clock. Once the transfer is complete, the INTS interrupt is generated, the PIN bit is cleared, and the SCL line is pulled low. To transmit further data, test the LRB bit again and repeat the above procedure. INTS interrupt if MST = 0 Then go to slave-mode processing if TRX = 0 Then go to receiver-mode processing if LRB = 0 Then go to processing for generating a STOP condition SBICR1 SBIDBR XXXX0 XXX XXXXXXXX Sets number of bits to be transmitted and specify whether ACK is required. Loads the transmit data. End of interrupt processing Note: X = Don't care SCL Pin Write to SBIDBR SDA Pin 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK Acknowledgement signal from receiver Master to Slave Slave to Master Figure 15.15 SBICR1.BC[2:0] = 000 and SBICR1.ACK = 1 (Master-Transmitter Mode) TMP1962-332 2006-02-21 TMP1962C10BXBG Master-Receiver mode (SBICR2.TRX = 0) If the number of bits per transfer is 8, read the SBIDBR. When using other data length, program the BC[2:0] and ACK bits in the SBICR1, and then read the SBIDBR. The first read of the SBIDBR is a dummy read because data has not yet been received. A dummy read returns an undefined value. Upon this read, the SCL line is released, the PIN bit in the SBISR is set, and the SCL clock is driven out to receive a data word into the SBIDBR. The master-transmitter generates an acknowledgement signal (i.e., a low level) on the SDA line following the last received bit. Once the transfer is complete, the INTS interrupt is generated, the PIN bit is cleared, and the SCL line is pulled low. Each subsequent read from the SBIDBR is accompanied by an SCL clock pulse for a data word and an acknowledgement signal. Read of the received data SCL 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK Next D7 Acknowledgement signal to transmitter SDA Master to Slave Slave to Master Figure 15.16 SBICR1.BC[2:0] = 000 and SBICR1.ACK = 1 (Master-Receiver Mode) To prepare to terminate the data transfer, the master-receiver must clear the ACK bit in the SBICR1 immediately before the read of the second to last data word. This causes an acknowledge clock pulse to be suppressed on the last data word. When the transfer is complete, the INTS interrupt is generated. After interrupt processing, the INTS interrupt handler must set the BC[2:0] field in the SBICR1 to 001 and read the SBIDBR, so that a clock is generated on the SCL line once. With the ACK bit cleared, the master-receiver holds the SDA line high, which signals the end of transfer to the slave-transmitter. Then, the SBI generates the INTS interrupt again, whereupon the INTS interrupt service routine must generate a STOP condition to stop communication via the I2C bus. SCL 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 1 SDA Negative acknowledge (high) to transmitter Figure 15.17 Terminating Data Transmission in Master-Receiver Mode TMP1962-333 2006-02-21 TMP1962C10BXBG Example: When receiving N data words INTS interrupt (after data transmission) 76543210 SBICR1 Reg. XXXX0 XXX SBI0CBR Sets the number of bits to be received and specifies whether ACK is required. Dummy read End of interrupt INTS interrupt (first to (N-2)th data reception) 76543210 Reg. SBIDBR Reads the first to (N-2)th data words. End of interrupt INTS interrupt ((N-1)th data reception) 76543210 SBI0CR1 X X X 0 0 X X X Reg. SBIDBR End of interrupt Disables generation of acknowledgement clock. Reads the (N-1)th data word. INTS interrupt (Nth data reception) 76543210 SBI0CR1 0 0 1 0 0 X X X Reg. SBIDBR End of interrupt Generates a clock once. Reads the Nth data word. INTS interrupt (after completing data reception) Processing for generating STOP condition End of interrupt X = Don't care Terminates data transmission. TMP1962-334 2006-02-21 TMP1962C10BXBG (2) Slave mode (SBICR2.MST = 0) If the MST bit in the SBICR2 is cleared, the SBI is in Slave mode. In Slave mode, the SBI generates the INTS interrupt on four occasions: 1) when the SBI has received any slave address; 2) when the SBI has received a general-call address; 3) when a data transfer has been completed in response to a received slave address that matches its own address in the I2CAR; and 4) when a data transfer has been completed in response to a general-call. Also, if the SBI, as a master, loses arbitration for the I2C bus, it switches to Slave mode. If arbitration is lost during a data transfer, SCL continues to be generated until the data word is complete; then the INTS interrupt is generated. When the INTS interrupt occurs, the PIN bit in the SBISR is cleared, and the SCL line is pulled low. When the SBIDBR is read or written or when the PIN bit is set back to 1, the SCL line is released after a period of tLOW. Processing to be done in Slave mode varies, depending on whether or not the SBI has switched over to Slave mode as a result of lost arbitration. Test the AL, TRX, AAS and AD0 bits in the SBISR to determine the processing required, as summarized in Table 15.2 Example: When the received slave address matches the SBI's own address and the data direction bit is 1 INTS interrupt if TRX = 0 Then go to other processing if AL = 1 Then go to other processing if AAS = 0 Then go to other processing XXX10XXX SBIDBR X X X X 0 X X X SBICR1 Note: X = Don't care Specifies the number of bits to be transmitted. Loads the transmit data. TMP1962-335 2006-02-21 TMP1962C10BXBG Table 15.2 Processing in Slave Mode 1 1 1 0 State Arbitration was lost while the slave address was being transmitted, and the SBI received a slave address with the direction bit set transmitted by another master. In Slave-Receiver mode, the SBI received a slave address with the direction bit set transmitted by the master. In Slave-Transmitter mode, the SBI has completed a transmission of one data word. Processing Set the SBICR1.BC[2:0] field to the number of bits in a data word and write the transmit data into the SBIDBR. 0 1 0 0 0 Test the SBISR.LRB bit. If the LRB bit is set, that means the master-receiver does not require further data. Set the SBICR2.PIN bit to 1 and clear the TRX bit to 0 to release the bus. If the LRB bit is cleared, that means the master-receiver requires further data. Set the SBICR1.BC[2:0] field to the number of bits in the data word and write the transmit data to the SBIDBR. Read the SBIDBR (a dummy read) to set the SBICR2.PIN bit to 1, or write a 1 to this bit. 0 1 1 1/0 Arbitration was lost while a slave address was being transmitted, and the SBI received either a slave address with the direction bit cleared or a general-call address transmitted by another master. Arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. In Slave-Receiver mode, the SBI received either a slave address with the direction bit cleared or a general-call address transmitted by the master. In Slave-Receiver mode, the SBI has completed a reception of a data word. 0 0 0 1 1/0 0 1/0 Set the SBICR1.BC[2:0] field to the number of bits in the data word and read the received data from the SBIDBR. TMP1962-336 2006-02-21 TMP1962C10BXBG 15.6.4 Generating a STOP Condition When the SBISR.BB bit is set, setting the MST, TRX and PIN bits in the SBICR2 to 1 and clearing the BB bit in the same register causes the SBI to start a sequence for generating a STOP condition on the I2C bus. Do not alter the contents of these bits until the STOP condition is present on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released (high) again; when SCL is high, the SBI drives the SDA pin high to generate a STOP condition. 76543210 SBICR2 1 1 0 1 1 0 0 0 Generates a STOP condition. "1" STOP condition Figure 15.18 Generating a STOP Condition TMP1962-337 2006-02-21 TMP1962C10BXBG 15.6.5 Repeated START Condition A data transfer is always terminated by a STOP condition. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave or change the data direction without first generating a STOP condition. The following describes the steps required to generate a repeated START condition. First, clear the MST, TRX and BB bits in the SBICR2 and set the PIN bit in the same register to release the bus. This causes the SDA pin to be held high and the SCL pin to be released. Because no STOP condition is generated on the bus, other devices think that the bus is busy. Then, poll the SBISR.BB bit until it is cleared to ensure that the SCL pin is released. Next, poll the LRB bit until it is set to ensure that no other device is pulling the SCL bus line low. Once the bus is determined to be free this way, use the steps described in Section 15.6.2 to generate a START condition. To satisfy the minimum setup time of the START condition, at least 4.7-s wait period (in normal mode) must be created by software after the bus becomes free. 76543210 SBICR2 Then if SBISR X = Don't care "0" "1" SCL Bus Line SCL Pin SDA Pin 9 Note: Ensure that MST = 1 before writing a 0 to MST. When MST = 0, writing a 0 to MST does not enable a repeated start. Figure 15.19 Repeated START Condition TMP1962-338 2006-02-21 TMP1962C10BXBG 15.7 Description of Registers Used in Clock-Synchronous 8-Bit SIO Mode This section provides a summary of the registers which control clock-synchronous 8-bit SIO operation and provides its status information for monitoring. Serial Bus Interface Control Register 0 7 Bit Symbol SBICR0 Read/Write (0xFFFF_F254) Reset Value Function SBIEN R/W 0 SBI operation 0: Disable 1: Enable 6 5 4 3 2 1 0 SBIEN: Enables or disables the operation of the SBI. If the SBI is disabled, no clock pulses are supplied to the SBI registers other than the SBICR0, so that power consumption in the system can be reduced (only the SBICR0 can be read or written). To use the SBI, set the SBIEN bit to 1 before configuring other registers of the SBI. Once the SBI operates, all settings in its registers are held if it is disabled. Note: Bits 0 to 6 of the SBICR0 are read as 0. Serial Bus Interface Control Register 1 7 SBICR1 (0xFFFF_F253) Bit Symbol Read/Write Reset Value Function 0 Start transfer 0: Stop 1: Start 0 Abort transfer 0: Continue 1: Abort 6 SIOINH W 5 SIOM1 0 Transfer mode 4 SIOM0 0 3 2 SCK2 W 0 1 SCK1 0 0 SCK0 R/W 1 SIOS Serial clock frequency 00: Transmit mode 01: Reserved 10: Transmit/Receive mode 11: Receive mode On writes: SCK[2:0] = Serial clock frequency 000 n = 3 001 n = 4 010 n = 5 011 n = 6 100 n = 7 101 n = 8 110 n = 9 111 1.27 MHz 633 kHz 316 kHz 158 kHz 79 kHz 40 kHz Clock gear: System clock: fsys (= 40.5 MHz) fc/1 Frequency = fsys/4 [ Hz ] n 2 20 kHz External clock Note: Clear the SIOS bit and set the SIOINH bit before programming the transfer mode and serial clock frequency bits. Serial Bus Interface Data Buffer Register 7 SBIDBR (0xFFFF_F252) Bit Symbol Read/Write Reset Value DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (receive)/W (transmit) Undefined Figure 15.20 SIO Mode Registers TMP1962-339 2006-02-21 TMP1962C10BXBG Serial Bus Interface Control Register 2 7 SBICR2 (0xFFFF_F250) Bit Symbol Read/Write Reset Value Function 0 00: Port mode 01: SIO mode 10: I C Bus mode 11: Reserved 2 6 5 4 3 SBIM1 W 2 SBIM0 0 1 0 SBI Operating mode Serial Bus Interface Register 7 SBISR (0xFFFF_F250) Bit Symbol Read/Write Reset Value Function 0 Serial transfer status monitor 0: 6 5 4 3 SIOF R 2 SEF 0 Shift operation status monitor 0: Termi nated 1 0 Termi-nat 1: In ed progress 1: In progress Serial Bus Interface Baud Rate Register 0 7 SBIBR0 (0xFFFF_F257) Bit Symbol Read/Write Reset Value Function 6 I2SBI R/W 0 IDLE 0: Off 1: On 5 4 3 2 1 0 W Must be written as 0. Serial Bus Interface Baud Rate Register 1 7 SBIBR1 (0xFFFF_F256) Bit Symbol Read/Write Reset Value Function P4EN R/W 0 Internal clock 0: Off 1: On 6 5 4 3 2 1 0 Figure 15.21 SIO Mode Registers TMP1962-340 2006-02-21 TMP1962C10BXBG 15.7.1 Serial Clock (1) Clock source The clock source for SIO mode can be selected from internal and external clocks through the programming of the SCK[2:0] field in the SBICR1. Internal clocks One of the seven internal clocks can be used as a serial clock, which is driven onto the SCK pin. At the beginning of a transfer, the SCK clock will start out at logic high. If software is slow and the reading of the received data or the writing of the transmit data cannot keep up with the serial clock rate, the SBI automatically inserts a wait period, as shown below. During this period, the serial clock is temporarily stopped to suspend a shift operation. Automatically inserted wait period SCK Output 1 2 3 7 8 1 2 6 7 8 1 2 3 SO Output Writes of the transmit data a0 a a1 a2 a 5 a6 a7 b0 b b1 c b4 b5 b6 b7 c0 c1 c2 Figure 15.22 Automatic Wait Insertion External clock (SBICR1.SCK[2:0] = 111) If the SCK[2:0] field in the SBICR1 contains 111, the SBI uses an external clock supplied from the SCK pin as a serial clock. For proper shift operations, the clock high width and the clock low width must satisfy the following relationship. SCK Pin tSCK tSCKH tSCKL, tSCKH > 8/fsys Figure 15.23 Maximum External Clock Frequency TMP1962-341 2006-02-21 TMP1962C10BXBG (2) Shift edge types In Transmit mode, leading-edge shift is used. In Receive mode, trailing-edge shift is used. Leading-edge shift Every bit of SIO data is shifted by the leading edge of the serial clock (falling edge of SCK). Trailing-edge shift Every bit of SIO data is shifted by the trailing edge of the serial clock (rising edge of SCK). SCK Pin SO Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Shift Register 76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76 ******7 (a) Leading-Edge Shift SCK Pin SI Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Shift Register ******** 0******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing-Edge Shift *: Don't care Figure 15.24 Shift Edge Types TMP1962-342 2006-02-21 TMP1962C10BXBG 15.7.2 Transfer Modes The SBI supports three SIO transfer modes: Receive mode, Transmit mode and Transmit/Receive mode. The SIOM[1:0] field in the SBICR1 is used to select a transfer mode. (1) 8-Bit Transmit mode Configure the SIO interface in Transmit mode and write the transmit data into the SBIDBR. Then setting the SIOS bit in the SBICR1 initiates a transmission. The contents of the SBIDBR are moved to an internal shift register and then shifted out on the SO pin, with the least-significant bit (LSB) first, synchronous to the serial clock. Once the transmit data is transferred to the shift register, the SBIDBR becomes empty, and the buffer-empty interrupt (INTSBI) is generated. In Internal Clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS interrupt service routine provides the next transmit data to the SBIDBR. Once the SBIDBR is loaded, the SIO interface will automatically get out of the wait state. In External Clock mode, the INTS interrupt service routine must provide the next transmit data to the SBIDBR before the previous transmit data has been shifted out. Therefore, the data rate is a function of the maximum latency between when the INTS interrupt is generated and when the SBIDBR is loaded by the interrupt service routine. At the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the SO pin between when the SBISR.SIOF bit is set and when SCK subsequently goes low. Transmission can be terminated by the INTS interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, the remaining bits in the SBIDBR continue to be shifted out before transmission ends. In this case, software can check the SBISR.SIOF bit to determine whether transmission has come to an end (0 = end-of-transmission). If the SIOINH bit is set, the ongoing transmission is aborted immediately, and the SIOF bit is cleared at that point. In External Clock mode, the SIOS bit must be cleared before the SIO interface begins shifting out the next transmit data. Otherwise, the SIO will stop after sending out dummy data. 76543210 SBICR1 SBIDBR SBICR1 0 1 0 0 0 XXX XXXXXXXX 1 0 0 0 0 XXX Selects transmit mode. Writes the transmit data. Starts transmission. INTS interrupt SBIDBR XXXXXXXX Writes the next transmit data. TMP1962-343 2006-02-21 TMP1962C10BXBG The SIOS bit is cleared. The SIOS bit is cleared. Figure 15.25 Transmit Mode Example: MIP16 code to terminate transmission by SIOS (external clock mode) ADDIU STEST1: LB AND BNEZ ADDIU STEST2: LB AND BEQZ ADDIU STB r3, r2, r2, r3, r2, (PA) r2, r2, r3, r3 STEST2 r0, 0y00000111 ; r2, (SBISR) r3, (SBICR1) TMP1962-344 2006-02-21 TMP1962C10BXBG SCK Pin SIOF SO Pin bit 6 bit 7 tSODH = Min. 3.5/fsys/2 [s] Figure 15.26 Retention Time of the Last Transmitted Bit (2) 8-Bit Receive mode Configure the SIO interface in Receive mode. Then setting the SIOS bit in the SBICR1 enables reception. The receive data is clocked into the internal shift register via the SI pin, with the least-significant bit (LSB) first, synchronous to the serial clock. Once the shift register is fully loaded, the received byte is transferred to the SBIDBR, and the buffer-full interrupt (INTS0) is generated. The INTS interrupt service routine must then pick up the received data from the SBIDBR. In Internal Clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS interrupt service routine reads the data from the SBIDBR. In External Clock mode, shift operations continue, synchronous to the external clock. In this mode, the maximum data rate is a function of the maximum latency between when the INTS interrupt is generated and when the SBIDBR is read by the interrupt service routine. Reception can be terminated by the INTS interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the shift register is fully loaded and transferred to the SBIDBR. In this case, software can check the SBISR.SIOF bit to determine whether reception has come to an end (0 = end-of-reception). If the SIOINH bit is set, the ongoing reception is aborted immediately, and the SIOF bit is cleared at that point. (The received data becomes invalid; there is no need to read it out.) Note: The contents of the SBIDBR are not preserved after changing the transfer mode. Before changing the transfer mode, clear the SIOS bit to complete the ongoing reception and have the INTS interrupt service routine pick up the last received data. 76543210 SBICR1 SBICR1 0 1 1 1 0 XXX 1 0 1 1 0 0 0 0 Selects receive mode. Starts reception. INTS interrupt Reg. SBIDBR Reads the received data. TMP1962-345 2006-02-21 TMP1962C10BXBG The SIOS bit is cleared. Figure 15.27 Receive Mode (Internal Clock Mode) (3) 8-Bit Transmit/Receive mode Configure the SIO interface in Transmit/Receive mode and write the transmit data into the SBIDBR. Then setting the SIOS bit in the SBICR1 initiates transmission and reception. The transmit data is shifted out through the SO pin, with the least-significant bit (LSB) first, with the falling edge of the serial clock, while at the same time the receive data is shifted in through the SI pin with the rising edge of the serial clock. Once the shift register is fully loaded with eight bits of the received data, it is transferred to the SBIDBR, and the INTS interrupt is generated. The INTS interrupt service routine must then pick up the received data from the SBIDBR and writes the next transmit data into the SBIDBR. Because the SBIDBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In Internal Clock mode, the SIO interface will be in wait state (SCK will stop) after a read of the received data until a write of the transmit data. In External Clock mode, shift operations continue, synchronous to the external clock. Therefore, software must read the received data and write the transmit data before the next shift operation begins. In this mode, the maximum data rate is a function of the maximum latency between when the INTS interrupt is generated and when the interrupt service routine reads the received data and writes the transmit data. At the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the SO pin between when the SBISR.SIOF bit is set and when SCK subsequently goes low. Transmission/reception can be terminated by the INTS interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the shift register is fully loaded and transferred to the SBIDBR. In this case, software can check the SBISR.SIOF bit to determine whether transmission/reception has come to an end (0 = end-of-reception/transmission). If the SIOINH bit is set, the ongoing transmission/reception is aborted immediately, and the SIOF bit is cleared at that point. Note: The contents of the SBIDBR are not preserved after changing the transfer mode. Before changing the transfer mode, clear the SIOS bit to complete the ongoing transmission/reception and have the INTS interrupt service routine pick up the last received data. TMP1962-346 2006-02-21 TMP1962C10BXBG The SIOS bit is cleared. (b) Write of the transmit data (c) Read of the received data (d) Read of the received data Figure 15.28 Receive/Transmit Mode (Internal Clock Mode) SCK Output SIOF SO Pin bit 6 Bit 7 of the last byte transmitted tSODH = Min. 4/fsys/2 [s] Figure 15.29 Retention Time of the Transmit Data in Receive/Transmit Mode 76543210 SBICR1 SBIDBR SBICR1 0 1 1 0 0 XXX XXXXXXXX 1 0 1 0 0 XXX Selects receive/transmit mode. Writes the transmit data. Starts reception/transmission. INTS interrupt Reg. SBIDBR SBIODBR XXXXXXXX Reads the received data. Writes the transmit data. TMP1962-347 2006-02-21 TMP1962C10BXBG 16. Analog-to-Digital Converter (ADC) The TMP1962 has a 24-channel, multiplexed-input, 10-bit successive-approximation analog-to-digital converter (ADC). Figure 16.1 shows a block diagram of the ADC. The 24 analog input channels (AN0-AN23) can be used as general-purpose digital inputs if not needed as analog channels. Note: Please confirm the thing that the movement of the A/D converter has stopped when changing to IDLE and the STOP mode. Internal Data Bus Internal Data Bus Internal Data Bus ADS ADMOD1 ADSCN ADMOD0 ADMOD3 ADMOD4 end busy A/D Monitor Function Interrupt A/D Monitor Function Control A/D Start Control ADTRG TA0/CTRG Channel Selection Control Circuit scan repeat interrupt Interval Normal A/D Converter Control Circuit AN23 (P97) AN15 (P87) Multiplexer Interrupt Request (INTAD) AN7 (P77) - Comparator AN0 (P70) A/D Conversion Result Register VREF VREFH VREFL D/A Converter Figure 16.1 ADC Block Diagram TMP1962-348 Compare Register Sample-andHold + Compare Circuit A/D Conversion Result Registers ADREG08L~7FL ADREG08H~7FH 2006-02-21 TMP1962C10BXBG 16.1 Register Description The ADC has five mode control registers (ADMOD0,ADMMOD3,ADMOD4). Figure 16.2 to Figure 16.6 show the registers available in the ADC. A/D Mode Control Register 0 7 ADMOD0 (0xFFFF_F31B) Bit Symbol Read/Write Reset Value Function 0 End-of-conv ersion flag 6 ADBFN R 0 A/D conversion busy flag 5 4 ITM1 0 Interrupt in Fixed-Chan nel Continuous Conversion mode 3 ITM0 0 Interrupt in Fixed-Chan nel Continuous Conversion mode 2 REPEAT R/W 0 Continuous conversion mode 0: Single 1:Conti-nuous 1 SCAN 0 Channel scan mode 0 ADS 0 A/D conversion start EOCFN 0: During conver-sion 0: Idle 1:Comp-leted 1: During conver-sion 0:Fixed-Ch 0: Don't care annel 1: Start 1: Channel This bit is Scan always read as 0. Interrupt in Fixed-Channel Continuous Conversion mode Fixed-Channel Continuous Conversion Mode SCAN = 0, REPEAT = 1 00 01 10 Generates INTAD interrupt when a single conversion has been completed. Generates INTAD interrupt when a sequence of four conversions has been completed. Generates INTAD interrupt when a sequence of eight conversions has been completed. 11 Setting prohibited Figure 16.2 A/D Conversion Registers TMP1962-349 2006-02-21 TMP1962C10BXBG A/D Mode Control Register 1 7 ADMOD1 (0xFFFF_F31A) Bit Symbol Read/Write Reset Value Function 0 VREF control 0: Off 1: On 0 IDLE 0: Off 1: On 0 0 VREFON 6 I2AD 5 ADSCN 4 ADCH4 R/W 3 ADCH3 0 2 ADCH2 0 1 ADCH1 0 0 ADCH0 0 Channel Analog input channel select scan mode 0: 4-channel 1: 8-channel Analog input channel select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 10000 10001 10010 10011 10100 10101 10110 10111 0 Fixed-Channel Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 1 1 Channel Scan Mode Channel Scan Mode (ADSCN = 0) (ADSCN = 1) AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 AN4 AN4 to AN5 AN4 to AN6 AN4 to AN7 AN8 AN8 to AN9 AN8 to AN10 AN8 to AN11 AN12 AN12 to AN13 AN12 to AN14 AN12 to AN15 AN16 AN16 to AN17 AN16 to AN18 AN16 to AN19 AN20 AN20 to AN21 AN20 to AN22 AN20 to AN23 AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 AN0 to AN4 AN0 to AN6 AN0 to AN6 AN0 to AN7 AN8 AN8 to AN9 AN8 to AN10 AN8 to AN11 AN8 to AN12 AN8 to AN13 AN8 to AN14 AN8 to AN15 AN16 AN16 to AN17 AN16 to AN18 AN16 to AN19 AN16 to AN20 AN16 to AN21 AN16 to AN22 AN16 to AN23 Note 1: Set the VREFON bit to 1 before a conversion is started, i.e., before setting the ADS bit in the ADMOD0 or before an external trigger is activated. Note 2: If the TMP1962 will enter a standby mode upon the completion of A/D conversion, clear the VREFON bit to 0. Figure 16.3 A/D Conversion Registers TMP1962-350 2006-02-21 TMP1962C10BXBG A/D Mode Control Register 3 7 ADMOD3 (0xFFFF_F318) Bit Symbol Read/Write Reset Value Function R/W 0 Must be written as 0. 0 A/D monitor interrupt setting 0: Less than compare register 1: Greater than compare register 0 Must be written as 0. 0 6 5 ADOBIC 4 3 REGS2 R/W 2 REGS1 0 1 REG 0 0 0 ADOBSV 0 A/D monitor function 0: Disable 1: Enable A/D conversion result register to be compared with compare register when A/D monitor function is enabled 0000 0001 0010 0011 0100 0101 0110 0111 Target A/D Conversion Result Register ADREG08 ADREG ADREG ADREG ADREG ADREG ADREG 9 A B C D E ADREG7F A/D Mode Control Register 4 7 ADMOD4 (0xFFFF_F31F) Bit Symbol Read/Write Reset Value Function 0 Must be written as 0. R/W 0 Hardware trigger source conversion 0: External trigger 1: TA0TRG 6 5 ADHS 4 ADHTG 0 Hardware trigger conversion 0: Disable 1: Enable 3 2 1 ADRST1 W Software reset 0 ADRST0 W A write of 10 followed by a write of 01 Note 1: When enabling an external resource to trigger A/D conversion, set the PI0F bit in the PIFC to 1, thus configuring the PI0 pin as ADTRG , before setting the ADHTG bit. When using an 8-bit timer as a trigger, first set the ADHS bit to 1 when the timer is not operating. Then, set the ADHTG bit to enable trigger operation. Finally, operate the timer so that A/D conversion will be initiated at constant intervals. Note 2: When disabling an external trigger ( ADTRG ) for A/D conversion, first clear the ADHTG bit to 0. TMP1962-351 2006-02-21 TMP1962C10BXBG A/D Conversion Result Low Register 08 7 ADREG08L (0xFFFF_F303) Bit Symbol Read/Write Reset Value Function ADR01 R Undefined Lower 2 bits of an A/D conversion result 6 ADR00 5 4 3 2 1 OVR0 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR0RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 08 7 ADREG08H (0xFFFF_F302) Bit Symbol Read/Write Reset Value Function ADR09 6 ADR08 5 ADR07 4 ADR06 R Undefined 3 ADR05 2 ADR04 1 ADR03 0 ADR02 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 19 7 ADREG19L (0xFFFF_F301) Bit Symbol Read/Write Reset Value Function Lower 2 bits of an A/D conversion result ADR11 R 6 ADR10 5 4 3 2 1 OVR1 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR1RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 19 7 ADREG19H (0xFFFF_F300) Bit Symbol Read/Write Reset Value Function ADR19 6 ADR18 5 ADR17 4 ADR16 R Undefined 3 ADR15 2 ADR14 1 ADR13 0 ADR12 Upper 8 bits of an A/D conversion result 9 Channel x conversion result bits 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 2 ADREGxL 1 0 * Bits 5-2 are always read as 1. * Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when the ADREGxL is read. * Bit 1 (OVRx) indicates an overrun error. This bit is set if a next conversion result is written to the ADREGxH/L before both the ADREGxH and ADREGxL are read. Reading the flag causes it to be cleared. Figure 16.4 A/D Conversion Registers TMP1962-352 2006-02-21 TMP1962C10BXBG A/D Conversion Result Low Register 2A 7 ADREG2AL (0xFFFF_F307) Bit Symbol Read/Write Reset Value Function ADR21 R Undefined Lower 2 bits of an A/D conversion result 6 ADR20 5 4 3 2 1 OVR2 R 0 Overrun flag 0: No overrun 0 ADR2RF R 0 Conversion result store flag 1: Stored 1: Overrun A/D Conversion Result High Register 2A 7 ADREG2AH (0xFFFF_F306) Bit Symbol Read/Write Reset Value Function ADR29 6 ADR28 5 ADR27 4 ADR26 R Undefined 3 ADR25 2 ADR24 1 ADR23 0 ADR22 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 3B 7 ADREG3BL (0xFFFF_F305) Bit Symbol Read/Write Reset Value Function ADR31 R Undefined Lower 2 bits of an A/D conversion result 6 ADR30 5 4 3 2 1 OVR3 R 0 Overrun flag 0: No overrun 0 ADR3RF R 0 Conversion result store flag 1: Stored 1: Overrun A/D Conversion Result High Register 3B 7 ADREG3BH (0xFFFF_F304) Bit Symbol Read/Write Reset Value Function ADR39 6 ADR38 5 ADR37 4 ADR36 R Undefined 3 ADR35 2 ADR34 1 ADR33 0 ADR32 Upper 8 bits of an A/D conversion result 9 Channel x conversion result bits 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 2 ADREGxL 1 0 * Bits 5-2 are always read as 1. * Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when the ADREGxL is read. * Bit 1 (OVRx) indicates an overrun error. This bit is set if a next conversion result is written to the ADREGxH/L before both the ADREGxH and ADREGxL are read. Reading the flag causes it to be cleared. Figure 16.5 A/D Conversion Registers TMP1962-353 2006-02-21 TMP1962C10BXBG A/D Conversion Result Low Register 4C 7 ADREG4CL (0xFFFF_F30B) Bit Symbol Read/Write Reset Value Function ADR41 R Undefined Lower 2 bits of an A/D conversion result 6 ADR40 5 4 3 2 1 OVR4 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR4RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 4C 7 ADREG4CH (0xFFFF_F30A) Bit Symbol Read/Write Reset Value Function ADR49 6 ADR48 5 ADR47 4 ADR46 R Undefined 3 ADR45 2 ADR44 1 ADR43 0 ADR42 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 5D 7 ADREG5DL (0xFFFF_F309) Bit Symbol Read/Write Reset Value Function ADR51 R Undefined Lower 2 bits of an A/D conversion result 6 ADR50 5 4 3 2 1 OVR5 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR5RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 5D 7 ADREG5DH (0xFFFF_F308) Bit Symbol Read/Write Reset Value Function ADR59 6 ADR58 5 ADR57 4 ADR56 R Undefined 3 ADR55 2 ADR54 1 ADR53 0 ADR52 Upper 8 bits of an A/D conversion result 9 Channel x conversion result bits 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 ADREGxL 2 1 0 * Bits 5-2 are always read as 1. * Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when the ADREGxL is read. * Bit 1 (OVRx) indicates an overrun error. This bit is set if a next conversion result is written to the ADREGxH/L before both the ADREGxH and ADREGxL are read. Reading the flag causes it to be cleared. TMP1962-354 2006-02-21 TMP1962C10BXBG A/D Conversion Result Low Register 6E 7 ADREG6EL (0xFFFF_F30F) Bit Symbol Read/Write Reset Value Function ADR61 R Undefined Lower 2 bits of an A/D conversion result 6 ADR60 5 4 3 2 1 OVR6 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR6RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 6E 7 ADREG6EH (0xFFFF_F30E) Bit Symbol Read/Write Reset Value Function ADR69 6 ADR68 5 ADR67 4 ADR66 R Undefined 3 ADR65 2 ADR64 1 ADR63 0 ADR62 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 7F 7 ADREG7FL (0xFFFF_F30D) Bit Symbol Read/Write Reset Value Function ADR71 R Undefined Lower 2 bits of an A/D conversion result 6 ADR70 5 4 3 2 1 OVR7 R 0 Overrun flag 0: No overrun 1: Overrun 0 ADR7RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 7F 7 ADREG7FH (0xFFFF_F30C) Bit Symbol Read/Write Reset Value Function ADR79 6 ADR78 5 ADR77 4 ADR76 R Undefined 3 ADR75 2 ADR74 1 ADR73 0 ADR72 Upper 8 bits of an A/D conversion result 9 Channel x conversion result bits 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 ADREGxL 2 1 0 * Bits 5-2 are always read as 1. * Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when the ADREGxL is read. * Bit 1 (OVRx) indicates an overrun error. This bit is set if a next conversion result is written to the ADREGxH/L before both the ADREGxH and ADREGxL are read. Reading the flag causes it to be cleared. TMP1962-355 2006-02-21 TMP1962C10BXBG A/D Conversion Result Compare Low Register 7 ADCOMREGL (0xFFFF_F317) Bit Symbol Read/Write Reset Value Function ADR21 R/W 0 Lower 2 bits of a value to be compared with an A/D conversion result 6 ADR20 5 4 3 2 1 0 A/D Conversion Result Compare High Register 7 ADCOMREGH (0xFFFF_F316) Bit Symbol Read/Write Reset Value Function ADR29 6 ADR28 5 ADR27 4 ADR26 R/W 0 3 ADR25 2 ADR24 1 ADR23 0 ADR22 Upper 8 bits of a value to be compared with an A/D conversion result Note: Disable the A/D monitor function (set ADMOD3.ADOBSV to 0) before attempting to set or modify the contents of these registers. TMP1962-356 2006-02-21 TMP1962C10BXBG A/D Conversion Clock Setting Register 7 ADCLK (0xFFFF_F31C) Bit Symbol Read/Write Reset Value Function 6 5 4 3 2 ADCLK2 R/W 0 000: fc 001: fc/2 010: fc/4 011: fc/8 1 ADCLK1 R/W 0 1XX: fc/16 0 ADCLK0 R/W 0 A/D prescaler output Note 1: A/D conversion is performed at the clock frequency selected in the above register. To assure conversion accuracy, however, the conversion clock frequency must not exceed 20.25 MHz. Fc = 40.5MHz ADDCLK2:0 /1 /2 /4 /8 /16 ADCLK Figure 16.6 A/D Conversion Registers TMP1962-357 2006-02-21 TMP1962C10BXBG 16.2 Operation 16.2.1 Analog Reference Voltages The VREFH and VREFL pins provide the reference voltages for the ADC. Clearing the VREFON bit in the ADMOD1 turns off the switch between VREFH and VREFL. Once the VREFON bit is cleared, the internal reference voltage requires a recovery time of 3 s (T.B.D.) to stabilize after the VREFON bit is again set to 1. The ADS bit in the ADMOD0 must then be set to initiate an conversion. * Fixed-Channel mode (ADMOD0.SCAN = 0) When the SCAN bit in the ADMOD0 is cleared, the ADC runs conversions on a single input channel selected from AN0-AN23 via the ADCH[4:0] field in the ADMOD1. * Channel Scan mode (ADMOD0.SCAN = 1) When the SCAN bit in the ADMOD0 is set, the ADC runs conversions on sequential channels in a specific group selected via the ADCH[4:0] field in the ADMOD1. After a reset, the ADMOD0.SCAN bit defaults to 0, and the ADMOD1.ADCH[3:0] field defaults to 0000. Thus, the AN0 pin is selected as the conversion channel. The AN0-AN23 pins can be used as general-purpose input ports if not used as analog input channels. 16.2.2 Starting an A/D Conversion The ADC initiates conversion when the ADS bit in the ADMOD0 is set. The ADHTG bits in the ADMOD4 enable a hardware trigger source for conversion, respectively. When the ADHS bit in the ADMOD4 is cleared to 0, conversion is triggered by a falling edge applied to ADTRG pin. When the ADHS bit is set to 1, conversion is triggered by a TA0TRG output from 8-Bit Timer 0. When conversion starts, the busy flag (ADMOD0.ADBF) is set. . TMP1962-358 2006-02-21 TMP1962C10BXBG 16.2.3 Conversion Modes and Conversion-Done Interrupts The ADC supports the following four conversion modes. For a normal A/D conversion, the REPEAT and SCAN bits in the ADMOD0 select one of the four conversion modes. For a high-priority A/D conversion, the ADC only supports Fixed-Channel Single Conversion mode, regardless of the settings of the REPEAT and SCAN bits. * * * * Fixed-Channel Single Conversion mode Channel Scan Single Conversion mode Fixed-Channel Continuous Conversion mode Channel Scan Continuous Conversion mode The REPEAT and SCAN bits in the ADMOD0 select the conversion mode. Once a conversion is started, the ADBFN bit in the ADMOD0 is set to 1. The ADC generates the INTAD interrupt and sets the EOCF bit in the ADMOD0 at the end of the specified conversion process. If REPEAT = 0, the ADBFN bit is cleared when the ADC sets the EOCF bit. If REPEAT = 1, the ADC continues conversion without clearing ADBFN. 1) Fixed-Channel Single Conversion mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 00. In this mode, the ADC performs a single conversion on a single selected channel. When a conversion is completed, the ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates the INTAD interrupt. The EOCF bit is cleared when it is read. 2) Channel Scan Single Conversion mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 01. In this mode, the ADC performs a single conversion on each of a selected group of channels. When a single conversion sequence is completed, the ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates the INTAD interrupt. The EOCF bit is cleared when it is read. 3) Fixed-Channel Continuous Conversion mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 10. In this mode, the ADC repeatedly converts a single selected channel. When a conversion process is completed, the ADC sets the ADMOD.EOCF bit. The ADMOD0.ADBF bit remains set. The ITM[1:0] bits in the ADMOD0 control interrupt generation in this mode. The timing when the EOCF bit is set also depends on the ITM[1:0] bits. The EOCF bit is cleared when it is read. If the ITM[1:0] field is set to 00, the ADC generates an interrupt after each conversion. The results of conversion are always stored in the ADREG08 register pair. The EOCF bit is set when the ADC stores the results in the ADREG08. If the ITM[1:0] field is set to 01, the ADC generates an interrupt after every four conversions. The results of conversions are sequentially stored in the ADREG08 to ADREG3B register pairs, in that order. The EOCF bit is set when the ADC stores the results in the ADREG3B. The next conversion results are again stored in the ADREG08, and so on. The EOCF bit is cleared when it is read. TMP1962-359 2006-02-21 TMP1962C10BXBG If the ITM[1:0] field is set to 10, the ADC generates an interrupt after every eight conversions. The results of conversions are sequentially stored in the ADREG08 to ADREG7F register pairs, in that order. The EOCF bit is set when the ADC stores the results in the ADREG7F. The next conversion results are again stored in the ADREG08, and so on. The EOCF bit is cleared when it is read. 4) Channel Scan Continuous Conversion mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 11. In this mode, the ADC repeatedly converts the selected group of channels. When a single conversion sequence is completed, the ADC sets the ADMOD0.EOCF bit and generates the INTAD interrupt. The ADMOD0.ADBF bit remains set. The EOCF bit is cleared when it is read. In continuous conversion modes (3) and 4)), clearing the ADMOD0.REPEAT bit stops the conversion sequence after the ongoing conversion process is completed. The ADMOD0.ADBF bit is cleared. Before putting the TMP1962 in any standby mode (IDLE or STOP), check the ADC is being disabled (or disable the ADC). TMP1962-360 2006-02-21 TMP1962C10BXBG Interrupt Request Generation and Flag Setting in Each A/D Conversion Mode Interrupt Request Generation After a conversion After every conversion After every four conversions After every eight conversions Channel Scan Single Conversion Mode Channel Scan Continuous Conversion Mode After a scan conversion sequence After each scan conversion sequence Mode EOCF Set Timing (Note) After a conversion After every conversion After every four conversions After every eight conversions After a scan conversion sequence After each scan conversion sequence ADBF (Upon Generation of Interrupt) 0 1 1 1 ADMOD0 ITM1:0 REPEAT 0 00 01 10 1 0 SCAN 0 Fixed-Channel Single Conversion Mode Fixed-Channel Continuous Conversion Mode 0 0 1 1 1 1 Note: EOCF is cleared when it is read. 16.2.4 High-Priority Conversion Mode The ADC can perform a high-priority A/D conversion while it is performing a normal A/D conversion sequence. A high-priority A/D conversion can be initiated by setting the HPADCE bit in the ADMOD2 to 1. It is also triggered by a hardware resource if so enabled using the HADHTG and HADHS bits in the ADMOD4. If a high-priority conversion is triggered during a normal conversion, the ADC stores the results of conversion for the current channel and then begins a single high-priority conversion for the channel specified with the HPADCH[4:0] bits in the ADMOD2. Upon the completion of the high-priority conversion, the ADC stores the results of the conversion in the ADREGSP, generates the end-of-high-priority-conversion interrupt, and then resumes the suspended normal conversion with the next channel. While a high-priority conversion is being performed, a trigger for another high-priority conversion is ignored. For example, suppose the ADC is performing conversions for AN0-AN8 in Channel Scan Continuous Conversion mode. If the HPADCE bit is set to 1 while the ADC is converting data for AN3, it completes conversion for AN3 and then converts data for the channel specified with HPADCH[4:0]. After storing the results of conversion in the ADREGSP, the ADC resumes the suspended normal conversion sequence, beginning with conversion for AN4. 16.2.5 A/D Monitor Function When the ADOBSV bit in the ADMOD3 is set to 1, the A/D monitor function is enabled. This function generates an interrupt if the value stored in the specified A/D conversion result register pair (specified with the REGS[3:0] bits in the ADMOD3) is greater or less (depending on ADMOD3.ADOBIC) than the contents of the compare register pair. The ADC performs this comparison each time it stores results to the specified register pair. The conversion result register pair used for the A/D monitor function is usually not read in the program, so that its overrun flag (OVRn) and conversion result storage flag (ADRnRF) are always set. When using the A/D monitor function, therefore, do not use flags for the register pair assigned for comparison. TMP1962-361 2006-02-21 TMP1962C10BXBG 16.2.6 Conversion Time The A/D conversion clock can be selected from A/D prescaler output T0/2, T0/4, T0/8, T0/16 and T0/32 through the programming of the ADCLK[2:0] field in the ADCLK register. To assure conversion accuracy, the conversion clock frequency must not exceed 20.25 MHz, i.e., conversion time must be no shorter than 7.95 s. 16.2.7 Storing and Reading the A/D Conversion Result Conversion results are loaded into conversion result high/low register pairs (ADREG08H/L to ADREG7FH/L). In Fixed-Channel Continuous Conversion mode, conversion data goes into the ADREG08H/L to ADREG7FH/L sequentially. If the ITM[1:0] field is set to 00, so that the ADC generates an interrupt after each conversion, conversion data is stored in the ADREG08H/L only. If the ITM[1:0] field is set to 01, so that the ADC generates an interrupt after every four conversions, conversion data goes into the ADREG08H/L to ADREG3BH/L sequentially. Table 16.1 shows the relationships between the analog input channels and the A/D conversion result registers. Table 16.1 Relationships Between Analog Input Channels and A/D Conversion Result Registers A/D Conversion Result Registers Analog Input Channel Fixed-Channel Continuous Modes Other Than Fixed-Channel (Port A) Conversion Mode (for each Continuous Conversion Mode sequence of eight conversions) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 ADREG08H/L ADREG19H/L ADREG2AH/L ADREG3BH/L ADREG4CH/L ADREG5DH/L ADREG6EH/L ADREG7FH/L ADREG08H/L ADREG19H/L ADREG2AH/L ADREG3BH/L ADREG4CH/L ADREG5DH/L ADREG6EH/L ADREG7FH/L ADREG08H/L ADREG19H/L ADREG2AH/L ADREG3BH/L ADREG4CH/L ADREG5DH/L ADREG6EH/L ADREG7FH/L ADREG7FH/L ADREG08H/L TMP1962-362 2006-02-21 TMP1962C10BXBG 16.2.8 Data Polling When the results of A/D conversion are processed by means of data polling without using interrupts, the EOCF bit in the ADMOD0 should be polled. If this flag is set, the specified A/D conversion result register pairs contain results. Then, read those registers. To detect an overrun, first read the ADREGxH and then read the ADREGxL. If the OVRn is cleared to 0 and ADRnRF is set to 1 in the ADREGxL, the register pair contains valid conversion results. TMP1962-363 2006-02-21 TMP1962C10BXBG 17. Watchdog Timer (WDT) The TMP1962 contains a watchdog timer (WDT). The WDT is used to regain control of the system in the event of software or system lockups due to spurious noises, etc. When a watchdog timer time-out occurs, the WDT generates a nonmaskable interrupt to the CPU. Also, the time-out event can be programmed for system reset generation, which is accomplished by routing the time-out signal to the internal reset pin. 17.1 Implementation Figure 17.1 shows a block diagram of the WDT. WDMOD RESET Pin Reset Control Internal Reset Interrupt Request (INTWDT) WDMOD 15 Selector 2 17 2 19 2 21 22-Stage Binary Counter Reset Q R S Internal Reset Write of 4EH Write of WDMOD Watchdog Timer Control Register (WDCR) Internal Data Bus Figure 17.1 WDT Block Diagram TMP1962-364 2006-02-21 TMP1962C10BXBG The WDT contains a 22-stage binary counter clocked by the fSYS/2 clock. This binary counter provides 215, 217, 219 or 221 as a counter overflow signal, as programmed into the WDTP[1:0] field in the WDMOD. When a counter overflow occurs, the WDT generates a WDT interrupt, as shown below. WDT Counter n Overflow 0 WDT Interrupt A write of a special clear-count code WDT Clear (via software) Figure 17.2 Default Operation Also, the counter overflow can be programmed to cause a system reset as the time-out action. If so programmed, a counter overflow causes the WDT to assert the internal reset signal for a 22- to 29-state time. After a reset, the fSYS clock is generated by dividing the high-speed oscillator clock (fc) by eight through the clock gear function (when the PLL is used); the WDT clock source (fSYS/2) is derived from this fSYS clock. Overflow WDT Counter n WDT Interrupt Internal Reset 22-29 States (8.8~11.6 s @ fC = 40 MHz, fsys = 5 MHz, fsys/2 = 2.5 MHz) Figure 17.3 Reset Operation Note: The TMP1962 continues sampling the PLLOFF pin during a reset operation caused by the WDT. Therefore, the PLLOFF pin must be tied to either logic high or logic low. TMP1962-365 2006-02-21 TMP1962C10BXBG 17.2 Register Description The WDT is controlled by two registers called WDMOD and WDCR. 17.2.1 Watchdog Timer Mode Register (WDMOD) (1) Time-out period (WDMOD.WDTP[1:0]) This 2-bit field determines the duration of the WDT time-out interval. Upon reset, the WDTP[1:0] field defaults to 00. Figure 17.4 shows possible time-out periods. (2) WDT enable (WDMOD.WDTE) Upon reset, the WDTE bit is set to 1, enabling the WDT. To disable the WDT, the clearing of the WDTE bit must be followed by a write of a special key code (B1H) to the WDCR register. This prevents a "lost" program from disabling the WDT operation. The WDT can be re-enabled simply by setting the WDTE bit. (3) System reset (WDMOD.RESCR) This bit is used to program the WDT to generate a system reset on a time-out. Upon reset, this bit is cleared; thus the time-out does not cause a system reset. 17.2.2 Watchdog Timer Control Register (WDCR) This register is used to disable the WDT and to clear the WDT binary counter. * Disabling the WDT The WDT can be disabled by clearing the WDMOD.WDTE to 0 and then writing the special disable code (B1H) to the WDCR register. WDMOD WDCR 0 - - - - - - - 1 0 1 1 0 0 0 1 Clears the WDTE bit to 0. Writes the disable code (B1H) to the WDCR. * * Enabling the WDT The WDT can be enabled simply by setting the WDTE bit in the WDMOD to 1. Clearing the WDT counter Writing the special clear-count code (4EH) to the WDCR resets the binary counter to zero. The counting process begins again. WDCR 0 1 0 0 1 1 1 0 Writes the clear-count code (4EH) to the WDCR. Note: Writing the disable code (BIH) clears the binary counter. TMP1962-366 2006-02-21 TMP1962C10BXBG 7 WDMOD (0xFFFF_F093) Bit Symbol Read/Write Reset Value Function WDTE R/W 1 WDT enable 1: Enable 6 WDTP1 R/W 0 Time-out period 00: 2 /fSYS 01: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS 22 20 18 16 5 WDTP0 0 4 3 2 I2WDT R/W 0 IDLE 0: Off 1: On 1 RESCR 0 1: System reset by WDT 0 R/W 0 Must be written as 0. System reset 0 1 Internally routes the WDT time-out signal to the system reset Time-out period Clock Gear Value SYSCR1. GEAR[1:0] 00 (fc) 01 (fc/2) 10 (fc/4) 11 (fc/8) @ fc = 40.5 MHz Watchdog Timer Time-out Period WDMOD 1.6 ms 3.2 ms 6.5 ms 12.9 ms 01 6.5 ms 12.9 ms 25.9 ms 51.8 ms 10 25.9 ms 51.8 ms 104 ms 207 ms 11 104 ms 207 ms 414 ms 829 ms WDT enable 0 1 Disable Enable Figure 17.4 Watchdog Timer Mode Register 7 WDCR (0xFFFF_F092) Bit Symbol Read/Write Reset Value Function 6 5 4 W 3 2 1 0 B1H: WDT disable code 4EH: WDT clear-count code Special code B1H 4EH Other values WDT disable code WDT clear-count code Figure 17.5 Watchdog Timer Control Register TMP1962-367 2006-02-21 TMP1962C10BXBG 17.3 Operation The watchdog timer is a kind of timer that generates an interrupt request if it times out. The WDT allows the user to program the time-out period in the WDTP[1:0] field in the WDMOD register. While enabled, the software can reset the counter to zero at any time by writing a special clear-count code. If the software is unable to reset the counter before it reaches the time-out count, the WDT generates the INTWD interrupt. In response to the interrupt, the CPU jumps to a system recovery routine to regain control of the system. The WDT can also output a time-out signal to a peripheral device so that the device can respond to the problem. The WDT begins counting immediately after reset. When the TMP1962 goes into STOP mode, the WDT counter is reset to zero automatically and stops counting. The WDT continues counting while an off-chip peripheral has mastership of the bus (i.e., BUSAK = 0). In IDLE mode, the I2WDT bit in the WDMOD determines whether or not to disable the WDT. The I2WDT bit can be programmed before putting the TMP1962 in IDLE mode. Examples: (1) Clearing the WDT binary counter 76543210 WDCR 0 1 0 0 1 1 1 0 Writes the clear-count code (4EH) to the WDCR. (2) Programming the time-out interval to 218/fSYS 76543210 WDMOD 1 0 1 - - - - - (3) Disabling the watchdog timer 76543210 WDMOD WDCR 0 - - - - - - - 1 0 1 1 0 0 0 1 Clears the WDTE bit to 0. Writes the disable code (B1H) to the WDCR. TMP1962-368 2006-02-21 TMP1962C10BXBG 18. Key-Pressed Wake-up 18.1 Outline * The TMP1962 has 14 key input channels (KEY0-KEYD) that enable the pressing of a key to terminate STOP mode or trigger an external interrupt. These 14 interrupts are, however, assumed as the same interrupt source (as specified in the CG block) when sent to the Interrupt Controller (INTC). Each key input can be enabled or disabled individually using the KWUPSTn register. The interrupt sensitivity and polarity (rising-edge triggered, falling-edge triggered, high-level sensitive or low-level sensitive) can be specified individually for each key input using the KWUPSTn register. The interrupt service routine clears the key interrupt request through the KWUPCLR register. Each key input pin has an internal pull-up resistor, which can be enabled or disabled by programming bit 0 (PE) of the KWUPCNT. The settings of the PE and DPE bits apply to all 14 key inputs. * * * 18.2 Operation The TMP1962 has 14 key input pins (KEY0-KEYD). The KWUPEN bit in the CG's IMCGB1 register controls whether the key inputs are used to exit STOP mode or used as general-purpose interrupt sources. When KWUPEN is set to 1, all of KEY0-KEYD are used for STOP wake-up signaling. For each key input, the KEYnEN bit in the KWUPSTn must be programmed to either enable or disable interrupts and the KEYn[1:0] field in the same register must be programmed to specify signal sensitivity. The KWUP circuit block detects key inputs and transmits the results to the IMCGB1 register in the CG, identifying the high level as an active state. The EMCG[51:50] bits in the IMCGB1 must be set to 01 (high-level sensitive). The CG in turn transmits the results to the INTC, also identifying the high level as an active state. The INTC must also be programmed so that the corresponding interrupt is high-level sensitive (01). When the KWUPEN bit in the IMCGB1 register is cleared to 0 (default), all of KEY0 to KEYD are used as general-purpose interrupts. In that case, the CG does not need to be programmed; only the INTC must be programmed so that the interrupt is high-level sensitive. The KWUPSTn must also be programmed to enable interrupts and specify signal sensitivity. In the key interrupt service routine, writing 1010 to the KWUPCLR causes all key interrupt requests to be cleared. Note: If another key input is detected before the interrupt service routine clears the interrupt request corresponding to the first key input, the routine clears all interrupt requests simultaneously. If another key input is detected after the interrupt service routine clears the interrupt request corresponding to the first key input, the new key input triggers another key interrupt. 18.3 Pull-up Resistors Each key input pin has an internal pull-up resistor. When the KYPE bit in the KWUPCNT is set to 1, pull-up resistors for all key input pins (KEY0-KEYD) are enabled, except for the pins for which key input is disabled by clearing the KEYnEN bit in the KWUPSTn. TMP1962-369 2006-02-21 TMP1962C10BXBG (1) When using key input pins in static pull-up mode, the following procedures must be observed: * Initial setup after power-on 1) Program the KWUPCNT (KYPE = 1). 2) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 3) Wait until the pull-up resistors are disabled. 4) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 5) Clear the interrupt request with KWUPCLR. 6) Program the CG and INTC, as described in Chapter 6, "Interrupts." * Modifying an interrupt trigger for key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Modify an interrupt trigger in the KWUPSTn for each relevant key input. 3) Clear the interrupt request with KWUPCLR. 4) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). * Enabling additional key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 3) Wait until the pull-up resistors are disabled. 4) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 5) Clear the interrupt request with KWUPCLR. 6) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). (2) When using key input pins in dynamic pull-up mode, the following procedures must be observed: * Initial setup after power-on 1) Program the KWUPCNT (KYPE = 1, TnSn = desired interval). 2) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 3) Clear the interrupt request with KWUPCLR. 4) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 5) Program the CG and INTC, as described in Chapter 6, "Interrupts." * Modifying an interrupt trigger for key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Modify an interrupt trigger in the KWUPSTn for each relevant key input. 3) Clear the interrupt request with KWUPCLR. 4) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). * Enabling additional key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 3) Clear the interrupt request with KWUPCLR. 4) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 5) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). TMP1962-370 2006-02-21 TMP1962C10BXBG (3) When using key input pins without enabling pull-up resistors, the following procedures must be observed: * Initial setup after power-on 1) Program the KWUPCNT (KYPE = 1). 2) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 3) Clear the interrupt request with KWUPCLR. 4) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 5) Program the CG and INTC, as described in Chapter 6, "Interrupts." * Modifying an interrupt trigger for key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Modify an interrupt trigger in the KWUPSTn for each relevant key input. 3) Clear the interrupt request with KWUPCLR. 4) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). * Enabling additional key inputs 1) Disable key interrupts in the INTC (IMC1.IL6[2:0] = 000). 2) Specify an interrupt trigger in the KWUPSTn for each key input to be used. 3) Clear the interrupt request with KWUPCLR. 4) Set the KWUPSTn.KEYnEN bit to 1 for each key input to be used. 5) Enable key interrupts in the INTC (program IMC1.IL6[2:0] as required). Key-Pressed Wake-up Control Register: KWUPCNT 7 (0xFFFF_F372) Bit Symbol Read/Write Reset Value Function R/W 0 Must be written as 0. 0 0 0 Must be set to 00. R/W 0 0 Must be set to 0. 0 0: Disable pull-up 1: Enable pull-up Must be set to 00. 6 5 4 3 2 1 0 KYPE 18.4 Key Input Detection Timing (1) When pull-up registers are disabled (KYPE = 0) For each key input, the KEYn[1:0] bits in the KWUPSTn register can specify one of four interrupt trigger types: high level, low level, rising edge and falling edge. The states of key inputs are always monitored. (2) When pull-up registers are enabled (KYPE = 1) For each key input, the KEYn[1:0] bits in the KWUPSTn register can specify one of four interrupt trigger types: high level, low level, rising edge and falling edge. The states of key inputs are always monitored. 7 KWUPST0 (0xFFFF_F363) Bit Symbol Read/Write 6 5 KEY01 R/W 4 KEY00 3 2 1 0 KEY0EN R/W TMP1962-371 2006-02-21 TMP1962C10BXBG Reset Value Function 1 0 KEY0 interrupt trigger 00: Low level 01: High level 10: Falling level 11: Rising level 0 KEY0 interrupt input 0: Disable 1: Enable 7 KWUPST1 (0xFFFF_F362) Bit Symbol Read/Write Reset Value Function 6 5 KEY11 R/W 4 KEY10 3 2 1 0 KEY1EN R/W 0 KEY1 interrupt input 0: Disable 1: Enable 1 0 KEY1 interrupt trigger 00: Low level 01: High level 10: Falling level 11: Rising level 7 KWUPST (0xFFFF_F361) Bit Symbol Read/Write Reset Value Function 6 5 KEY21 R/W 4 KEY20 3 2 1 0 KEY2EN R/W 0 KEY2 interrupt input 0: Disable 1: Enable 1 0 KEY2 interrupt trigger 00: Low level 01: High level 10: Falling level 11: Rising level 7 KWUPST3 (0xFFFF_F360) Bit Symbol Read/Write Reset Value Function 6 5 KEY31 R/W 4 KEY30 3 2 1 0 KEY3EN R/W 0 KEY3 interrupt input 0: Disable 1: Enable 1 0 KEY3 interrupt trigger 00: Low level 01: High level 10: Falling level 11: Rising level 7 KWUPST4 (0xFFFF_F367) Bit Symbol Read/Write Reset Value Function 6 5 KEY41 R/W 4 KEY40 3 2 1 0 KEY4EN R/W 0 KEY4 interrupt input 0: Disable 1: Enable 1 0 KEY4 interrupt trigger 00: Low level 01: High level 10: Falling level 11: Rising level TMP1962-372 2006-02-21 TMP1962C10BXBG 7 KWUPST5 (0xFFFF_F366) Bit Symbol Read/Write Reset Value Function 6 5 KEY51 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEY50 0 3 2 1 0 KEY5EN R/W 0 KEY5 interrupt input 0: Disable 1: Enable KEY5 interrupt trigger 7 KWUPST6 (0xFFFF_F365) Bit Symbol Read/Write Reset Value Function 6 5 KEY61 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEY60 0 3 2 1 0 KEY6EN R/W 0 KEY6 interrupt input 0: Disable 1: Enable KEY6 interrupt trigger 7 KWUPST7 (0xFFFF_F364) Bit Symbol Read/Write Reset Value Function 6 5 KEY71 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEY70 0 3 2 1 0 KEY7EN R/W 0 KEY7 interrupt input 0: Disable 1: Enable KEY7 interrupt trigger 7 KWUPST8 (0xFFFF_F36B) Bit Symbol Read/Write Reset Value Function 6 5 KEY81 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEY80 0 3 2 1 0 KEY8EN R/W 0 KEY8 interrupt input 0: Disable 1: Enable KEY8 interrupt trigger 7 KWUPST9 (0xFFFF_F36A) Bit Symbol Read/Write Reset Value Function 6 5 KEY91 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEY90 0 3 2 1 0 KEY9EN R/W 0 KEY9 interrupt input 0: Disable 1: Enable KEY9 interrupt trigger TMP1962-373 2006-02-21 TMP1962C10BXBG 7 KWUPSTA (0xFFFF_F369) Bit Symbol Read/Write Reset Value Function 6 5 KEYA1 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEYA0 0 3 2 1 0 KEYAEN R/W 0 KEYA interrupt input 0: Disable 1: Enable KEYA interrupt trigger 7 KWUPSTB (0xFFFF_F368) Bit Symbol Read/Write Reset Value Function 6 5 KEYB1 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEYB0 0 3 2 1 0 KEYBEN R/W 0 KEYB interrupt input 0: Disable 1: Enable KEYB interrupt trigger 7 KWUPSTC (0xFFFF_F36F) Bit Symbol Read/Write Reset Value Function 6 5 KEYC1 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEYC0 0 3 2 1 0 KEYCEN R/W 0 KEYC interrupt input 0: Disable 1: Enable KEYC interrupt trigger 7 KWUPSTD (0xFFFF_F36E) Bit Symbol Read/Write Reset Value Function 6 5 KEYD1 R/W 1 00: Low level 01: High level 10: Falling level 11: Rising level 4 KEYD0 0 3 2 1 0 KEYDEN R/W 0 KEYD interrupt input 0: Disable 1: Enable KEYD interrupt trigger 7 KWUPCLR (0xFFFF_F373) Bit Symbol Read/Write Reset Value Function 6 5 4 3 2 W 1 KEYCLR1 0 KEYCLR0 KEYCLR3 KEYCLR2 "1010" write of 00 clears all key interrupt requests TMP1962-374 2006-02-21 TMP1962C10BXBG 19. ROM Correction This chapter describes the ROM correction function supported by the TMP1962. 19.1 Features * * Up to eight 8-word sequences of data can be replaced. When the address stored in an address register (ADDREGn) matches the program counter (PC) value or the address generated by the DMAC (the lower five bits of the address are "don't care"), the data at the specified address in the on-chip ROM is replaced with the data from the RAM area corresponding to the address register. Writing an address to an address register causes ROM correction for the address to be enabled automatically. A correction requiring the replacement of more than eight words can also be performed by replacing the ROM data with an instruction code which makes a branch to a specified location in the RAM area which contains substitution data. * * 19.2 Operation To correct data in a ROM area (or a projected ROM area), store the physical start address of the area in an address register (ADDREG0-ADDREG7). Store the substitution data in the RAM area corresponding to the address register. Writing an address to an address register causes ROM correction for the address to be enabled automatically. Upon reset, the ROM correction function is disabled. If the initial routine executed upon reset is used to correct ROM data, write an address to the relevant address register after a reset is released. The address registers to which addresses are written are enabled for ROM correction. When the stored address matches the PC value (if the CPU has the bus right) or the source or destination address issued by the DMAC (if the DMAC has the bus right), the data at the specified address in the ROM is replaced with the data stored in the corresponding RAM area. For example, storing addresses in the ADDREG0 and ADDREG3 enables correction for the respective ROM areas, so that the ROM correction circuit block constantly monitors the PC and DMAC-issued addresses for a match with a specified address and, if a match is detected, replaces data, while ignoring the ADDREG2 and ADDREG4-ADDREG7. Each address register has bits 31:5 although only bits 19:5 are used for address comparison, in order to simplify the circuit. A match detected in the ROM correction circuit is internally ANDed with the ROMCS signal, which indicates a specified ROM address block, to determine an exact match. ROM addresses specified for correction must be located on eight-word boundaries, i.e., the lower five bits are 0. In other words, ROM data is always replaced in 32-byte units. If only part of 32 bytes need to be replaced, substitution RAM data corresponding to the other bytes must be the same as the current data in the corresponding ROM addresses. The following table shows the relationship between the address registers and RAM areas. Address Register ADDREG0 ADDREG1 ADDREG2 ADDREG3 ADDREG4 ADDREG5 ADDREG6 ADDREG7 RAM Area 0xFFFD_FF00 0xFFFD_FF1F 0xFFFD_FF20 0xFFFD_FF3F 0xFFFD_FF40 0xFFFD_FF5F 0xFFFD_FF60 0xFFFD_FF7F 0xFFFD_FF80 0xFFFD_FF9F 0xFFFD_FFA0 0xFFFD_FFBF 0xFFFD_FFC0 0xFFFD_FFDF 0xFFFD_FFE0 0xFFFD_FFFF TMP1962-375 2006-02-21 TMP1962C10BXBG G-Bus Address Registers ADDREGn ADDREGn Write Detection and Hold Circuit Compare Enable Converter RAM ROM Compare Circuit Selector Operand Address Instruction Address TX19 MPU Selector Operand Data Instruction Data GBIF Figure 19.1 ROM Correction Block Diagram TMP1962-376 2006-02-21 TMP1962C10BXBG 19.3 Registers (1) Address registers 7 ADDREG0 (0xFFFF_E540) Bit Symbol Read/Write Reset Value Function 0 0 ADD07 6 ADD06 5 ADD05 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD015 14 ADD014 0 13 ADD013 0 12 ADD012 0 R/W 11 ADD011 0 10 ADD010 0 9 ADD09 0 8 ADD08 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD023 22 ADD022 0 21 ADD021 0 20 ADD020 0 R/W 19 ADD019 0 18 ADD018 0 17 ADD017 0 16 ADD016 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD031 30 ADD030 0 29 ADD029 0 28 ADD028 0 R/W 27 ADD027 0 26 ADD026 0 25 ADD025 0 24 ADD024 0 7 ADDREG1 (0xFFFF_E544) Bit Symbol Read/Write Reset Value Function 0 ADD17 6 ADD16 0 5 ADD15 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD115 14 ADD114 0 13 ADD113 0 12 ADD112 0 R/W 11 ADD111 0 10 ADD110 0 9 ADD19 0 8 ADD18 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD123 22 ADD122 0 21 ADD121 0 20 ADD120 0 R/W 19 ADD119 0 18 ADD118 0 17 ADD117 0 16 ADD116 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD131 30 ADD130 0 29 ADD129 0 28 ADD128 0 R/W 27 ADD127 0 26 ADD126 0 25 ADD125 0 24 ADD124 0 TMP1962-377 2006-02-21 TMP1962C10BXBG 7 ADDREG2 (0xFFFF_E548) Bit Symbol Read/Write Reset Value Function 0 ADD27 6 ADD26 0 5 ADD25 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD215 14 ADD214 0 13 ADD213 0 12 ADD212 0 R/W 11 ADD211 0 10 ADD210 0 9 ADD29 0 8 ADD28 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD223 22 ADD222 0 21 ADD221 0 20 ADD220 0 R/W 19 ADD219 0 18 ADD218 0 17 ADD217 0 16 ADD216 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD231 30 ADD230 0 29 ADD229 0 28 ADD228 0 R/W 27 ADD227 0 26 ADD226 0 25 ADD225 0 24 ADD224 0 7 ADDREG3 (0xFFFF_E54C) Bit Symbol Read/Write Reset Value Function 0 ADD37 6 ADD36 0 5 ADD35 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD315 14 ADD314 0 13 ADD313 0 12 ADD312 0 R/W 11 ADD311 0 10 ADD310 0 9 ADD39 0 8 ADD38 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD323 22 ADD322 0 21 ADD321 0 20 ADD320 0 R/W 19 ADD319 0 18 ADD318 0 17 ADD317 0 16 ADD316 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD331 30 ADD330 0 29 ADD329 0 28 ADD328 0 R/W 27 ADD327 0 26 ADD326 0 25 ADD325 0 24 ADD324 0 TMP1962-378 2006-02-21 TMP1962C10BXBG 7 ADDREG4 (0xFFFF_E550) Bit Symbol Read/Write Reset Value Function 0 ADD47 6 ADD46 0 5 ADD45 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD415 14 ADD414 0 13 ADD413 0 12 ADD412 0 R/W 11 ADD411 0 10 ADD410 0 9 ADD49 0 8 ADD48 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD423 22 ADD422 0 21 ADD421 0 20 ADD420 0 R/W 19 ADD419 0 18 ADD418 0 17 ADD417 0 16 ADD416 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD431 30 ADD430 0 29 ADD429 0 28 ADD428 0 R/W 27 ADD427 0 26 ADD426 0 25 ADD425 0 24 ADD424 0 7 ADDREG5 (0xFFFF_E554) Bit Symbol Read/Write Reset Value Function 0 ADD57 6 ADD56 0 5 ADD55 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD515 14 ADD514 0 13 ADD513 0 12 ADD512 0 R/W 11 ADD511 0 10 ADD510 0 9 ADD59 0 8 ADD58 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD523 22 ADD522 0 21 ADD521 0 20 ADD520 0 R/W 19 ADD519 0 18 ADD518 0 17 ADD517 0 16 ADD516 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD531 30 ADD530 0 29 ADD529 0 28 ADD528 0 R/W 27 ADD527 0 26 ADD526 0 25 ADD525 0 24 ADD524 0 TMP1962-379 2006-02-21 TMP1962C10BXBG 7 ADDREG6 (0xFFFF_E558) Bit Symbol Read/Write Reset Value Function 0 ADD67 6 ADD66 0 5 ADD65 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD615 14 ADD614 0 13 ADD613 0 12 ADD612 0 R/W 11 ADD611 0 10 ADD610 0 9 ADD69 0 8 ADD68 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD623 22 ADD622 0 21 ADD621 0 20 ADD620 0 R/W 19 ADD619 0 18 ADD618 0 17 ADD617 0 16 ADD616 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD631 30 ADD630 0 29 ADD629 0 28 ADD628 0 R/W 27 ADD627 0 26 ADD626 0 25 ADD625 0 24 ADD624 0 7 ADDREG7 (0xFFFF_E55C) Bit Symbol Read/Write Reset Value Function 0 ADD77 6 ADD76 0 5 ADD75 R/W 0 4 3 2 1 0 15 Bit Symbol Read/Write Reset Value Function 0 ADD715 14 ADD714 0 13 ADD713 0 12 ADD712 0 R/W 11 ADD711 0 10 ADD710 0 9 ADD79 0 8 ADD78 0 23 Bit Symbol Read/Write Reset Value Function 0 ADD723 22 ADD722 0 21 ADD721 0 20 ADD720 0 R/W 19 ADD719 0 18 ADD718 0 17 ADD717 0 16 ADD716 0 31 Bit Symbol Read/Write Reset Value Function 0 ADD731 30 ADD730 0 29 ADD729 0 28 ADD728 0 R/W 27 ADD727 0 26 ADD726 0 25 ADD725 0 24 ADD724 0 Note 1: DMA transfer to an address register cannot be supported. DMA transfer to a substitution data area in the RAM is supported. The ROM correction function is supported when either the CPU or DMAC has an access right. Note 2: Writing the initial value 0x00 replaces the reset address. TMP1962-380 2006-02-21 TMP1962C10BXBG 20. DSU Interface The DSU interface is used for software debugging using an external DSU-probe unit. This serves as an interface to the DSU-probe, and cannot be used as a general-purpose port. Consult the DSU-probe operation manual for a description of debugging using a DSU-probe. (1) Security feature The TMP1962C10BXBG supports on-board debugging while it is installed on a printed circuit board. The TMP1962C10BXBG provides a security feature to prevent debugging. Unsecuring the device enables debugging with a DSU-probe. (2) Securing the device (Disabling debugging with a DSU-probe) The device is secured in the initial state. Debugging with a DSU-probe is disabled until the device is unsecured. (3) Unsecuring the device (Enabling debugging with a DSU-probe) The device may only be unsecured by clearing the SEQON bit in the SEQMOD register and then writing a special code (0x0000_00C5) to the Security Control (SEQCNT) register. This prevents runaway software from inadvertently turning off the security feature. However, a DSU-probe cannot read the contents of on-chip ROM or write to registers other than the processor core, on-chip memory and external device. When the device is reset, the device is secured until it is unsecured. 31 SEQMOD (0xFFFF_E510) Bit Symbol Read/Write Reset Value Function 30 29 28 27 26 25 24 23 Bit Symbol Read/Write Reset Value Function 22 21 20 19 18 17 16 15 Bit Symbol Read/Write Reset Value Function 14 13 12 11 10 9 8 7 Bit Symbol Read/Write Reset Value Function 6 5 4 3 2 1 0 SEQON R/W 1 1: Security on 0: Security off Note: This register must be read as a 32-bit quantity. Bits 1 to 31 are read as 0s. TMP1962-381 2006-02-21 TMP1962C10BXBG 31 SEQCNT (0xFFFF_E514) Bit Symbol Read/Write Reset Value Function 30 29 28 W 27 26 25 24 Must be written as 0x0000_00C5. 23 Bit Symbol Read/Write Reset Value Function 22 21 20 W 19 18 17 16 Must be written as 0x0000_00C5. 15 Bit Symbol Read/Write Reset Value Function 14 13 12 W 11 10 9 8 Must be written as 0x0000_00C5. 7 Bit Symbol Read/Write Reset Value Function 6 5 4 W 3 2 1 0 Must be written as 0x0000_00C5. Note: This register must be read as a 32-bit quantity. (4) Application example The following flowchart exemplifies how to use the security feature with a DSU-probe. TMP1962 Security on after a reset External port data, etc. Protect/unprotect judgement routine (user-created) No Turn off security feature? Yes Program SEQMOD and SEQCNT to turn off security feature DSU-probe cannot be used. Security remains on. DSU-probe can be used until the chip is powered off. Figure 20.1 Using the Security Feature TMP1962-382 2006-02-21 TMP1962C10BXBG 21. JTAG Interface The TMP1962 processor provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications, using the industry-standard JTAG protocol (IEEE Standard 1149.1/D6). This chapter describes that interface, including descriptions of boundary scanning, the pins and signals used by the interface, and the Test Access Port (TAP). 21.1 What Boundary Scanning Is With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and buried vias, in-circuit tests that depend upon making physical contact with internal board and chip connections have become more and more difficult to use. The greater complexity of ICs has also meant that tests to fully exercise these chips have become much larger and more difficult to write. One solution to this difficulty has been the development of boundary-scan circuits. A boundary-scan circuit is a series of shift register cells placed between each pin and the internal circuitry of the IC to which the pin is connected, as shown in Figure 21.1. Normally, these boundary-scan cells are bypassed; when the IC enters test mode, however, the scan cells can be directed by the test program to pass data along the shift register path and perform various diagnostic tests. To accomplish this, the tests use the four signals described in the next section: TDI, TDO, TMS, TCK, and TRST . Integrated Circuit C package pin Boundary-scan cells Figure 21.1 JTAG Boundary-scan Cells TMP1962-383 2006-02-21 TMP1962C10BXBG 21.2 Signal Summary The JTAG interface signals are listed below and shown in Figure 21.2. * * * * * TDI TDO TMS TCK TRST JTAG serial data in JTAG serial data out JTAG test mode select JTAG serial clock input JTAG test reset input 3 Instruction register 0 JTDI pin 0 JTD0 pin TAP Controller Bypass register JTMS pin 114 Boundary-scan register 0 JTCK pin TRST pin Figure 21.2 JTAG Interface Signals and Registers The JTAG boundary-scan mechanism (referred to in this chapter as JTAG mechanism) allows testing of the connections between the processor, the printed circuit board to which it is attached, and the other components on the circuit board. The JTAG mechanism does not provide any capability for testing the processor itself. TMP1962-384 2006-02-21 TMP1962C10BXBG 21.3 JTAG Controller and Registers The processor contains the following JTAG controller and registers: * * * * * Instruction register Boundary-scan register Bypass register ID Code register Test Access Port (TAP) controller The processor executes the standard JTAG EXTEST operation associated with External Test functionality testing. The basic operation of JTAG is for the TAP controller state machine to monitor the JTMS input signal. When it occurs, the TAP controller determines the test functionality to be implemented. This includes either loading the JTAG instruction register (IR), or beginning a serial data scan through a data register (DR), listed in Table 21.1. As the data is scanned in, the state of the JTMS pin signals each new data word, and indicates the end of the data stream. The data register to be selected is determined by the contents of the Instruction register. 21.3.1 Instruction Register The JTAG Instruction register includes eight shift register-based cells; this register is used to select the test to be performed and/or the test data register to be accessed. As listed in Table 21.1, this encoding selects either the Boundary-scan register or the Bypass register or Device Identification register. Table 21.1 JTAG Instruction Register Bit Encoding Instruction Code (MSB LSB) 0000 0001 0010 to 1110 1111 Instruction EXTEST SAMPLE/PRELOAD Reserved BYPASS Selected Data Register Boundary Scan Register Boundary Scan Register Reserved Bypass register Figure 21.3 shows the format of the Instruction register 3 MSB 2 1 0 LSB Figure 21.3 Instruction Register The instruction code is shifted out to the Instruction register from the LSB. MSB TDI LSB TDO Figure 21.4 Instruction Register Shift Direction TMP1962-385 2006-02-21 TMP1962C10BXBG 21.3.2 Bypass Register The Bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (Bypass) state, the data on the TDI pin is shifted into the Bypass register, and the Bypass register output shifts to the TDO output pin. In essence, the Bypass register is a short-circuit which allows bypassing of board-level devices, in the serial boundary-scan chain, which are not required for a specific test. The logical location of the Bypass register in the boundary-scan chain is shown in Figure 21.5. Use of the Bypass register speeds up access to boundary-scan registers in those ICs that remain active in the board-level test datapath. JTDI Bypass register Board input JTDO Board output JTDI JTDI JTDO JTDO JTDO JTDI JTDO JTDI Boundary-scan register pad cell IC package Board Figure 21.5 Bypass Register Operation 21.3.3 Boundary-Scan Register The Boundary Scan register includes all of the inputs and outputs of the TMP1962 processor, except some analog output and control signals. The pins of the TMP1962 chip can be configured to drive any arbitrary pattern by scanning into the Boundary Scan register from the Shift-DR state. Incoming data to the processor is examined by shifting while in the Capture-DR state with the Boundary Scan register enabled. The Boundary-scan register is a single, 115-bit-wide, shift register-based path containing cells connected to all input and output pads on the TMP1962 processor. The TDI input is loaded to the LSB of the Boundary Scan register. The MSB of the Boundary Scan register is retrieved from the JTDO output. TMP1962-386 2006-02-21 TMP1962C10BXBG 21.3.4 Test Access Port (TAP) The Test Access Port (TAP) consists of the five signal pins: TRST , TDI, TDO, TMS, and TCK. Serial test data and instructions are communicated over these five signal pins, along with control of the test to be executed. As Figure 21.6 shows, data is serially scanned into one of the three registers (Instruction register, Bypass register, or the Boundary-scan register) from the TDI pin, or it is scanned from one of these three registers onto the TDO pin. The TMS input controls the state transitions of the main TAP controller state machine. The TCK input is a dedicated test clock that allows serial JTAG data to be shifted synchronously, independent of any chip-specific or system clocks. TCK TMS and TDI sampled on rising edge of TCK Data scanned in serially 3 Instruction register 0 3 Instruction register TDO sampled on falling edge of TCK Data scanned out serially 0 0 Bypass register TDI pin 0 Bypass register TDO pin 115 0 TMS pin 115 0 Boundary-scan registe Boundary-scan register Figure 21.6 JTAG Test Access Port Data on the TDI and TMS pins is sampled on the rising edge of the TCK input clock signal. Data on the TDO pin changes on the falling edge of the TCK clock signal. 21.3.5 TAP Controller The processor implements the 16-state TAP controller as defined in the IEEE JTAC specification. 21.3.6 Controller Reset The TAP controller state machine can be put into Reset state the following: * * assertion of the TRST signal (Low) resets the TAP controller. keeping the TMS input signal asserted through five consecutive rising edges of TCK input. In either case, keeping TMS asserted maintains the Reset state. TMP1962-387 2006-02-21 TMP1962C10BXBG 21.3.7 TAP Controller The state transition diagram of the TAP controller is shown in Figure 21.7. Each arrow between states is labeled with a 1 or 0, indicating the logic value of TMS that must be set up before the rising edge of TCK to cause the transition. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 1 0 Capture-DR 0 Capture-IR 1 1 0 Shift-DR 0 0 Shift-IR 0 1 Exit 1-DR 1 1 Exit 1-IR 1 0 Pause-DR 0 0 Pause-IR 0 1 0 Exit 2-DR 0 1 Exit 2-IR 1 Update-DR 1 Update-IR 1 0 1 0 Figure 21.7 TAP Controller State Diagram The following paragraphs describe each of the controller states. The left vertical column in Figure 21.7 is the data column, and the right vertical column is the instruction column. The data column and instruction column reference data register (DR) and instruction register (IR), respectively. TMP1962-388 2006-02-21 TMP1962C10BXBG * Test-Logic-Reset When the TAP controller is in the Reset state, the Device Identification register is selected as default. The three most significant bits of the Boundary-scan register are cleared to 0, disabling the outputs. The controller remains in this state while TMS is high. If TMS is held low while the controller is in this state, then the controller moves to the Run-Test/Idle state. * Run-Test/Idle In the Run-Test/Idle state, the IC is put in a test mode only when certain instructions such as a built-in self test (BIST) instruction are present. For instructions that do not cause any activities in this state, all test data registers selected by the current instruction retain their previous states. The controller remains in this state while TMS is held low. When TMS is high, the controller moves to the Select-DR-Scan state. * Select-DR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the controller is in this state, then the controller moves to the Capture-DR state. If TMS is held high, the controller moves to the Select-IR-Scan state in the instruction column. * Select-IR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the controller is in this state, then the controller moves to the Capture-IR state. If TMS is held high, the controller returns to the Test-Logic-Reset state. * Capture-DR In this controller state, if the test data register selected by the current instruction on the rising edge of TCK has parallel inputs, then data can be parallel-loaded into the shift portion of the data register. If the test data register does not have parallel inputs, or if data need not be loaded into the selected data register, then the data register retains its previous state. If TMS is held low while the controller is in this state, the controller moves to the Shift-DR state. If TMS is held high, the controller moves to the Exit1-DR state. * Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data one stage forward towards its serial output. When the controller is in this state, then it remains in the Shift-DR state if TMS is held low, or moves to the Exit1-DR state if TMS is held high. TMP1962-389 2006-02-21 TMP1962C10BXBG * Exit 1-DR This is a temporary controller state. If TMS is held low when the controller is in this state, the controller moves to the Pause-DR state. If TMS is held high, the controller moves to the Update-DR state. * Pause-DR This state allows the shifting of the data register selected by the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the controller is in this state, then it remains in the Pause-DR state if TMS is held low, or moves to the Exit2-DR state if TMS is held high. * Exit 2-DR This is a temporary controller state. When the controller is in this state, then it returns to the Shift-DR state if TMS is held low, or moves on to the Update-DR state if TMS is held high. * Update-DR In this state, data is latched, on the falling edge of TCK, onto the parallel outputs of the data registers from the shift register path. The data held at the parallel output does not change while data is shifted in the associated shift register path. When the controller is in this state, it moves to either the Run-Test/Idle state if TMS is held low, or the Select-DR-Scan state if TMS is held high. * Capture-IR In this state, data is parallel-loaded into the instruction register. The two least significant bits are assigned the values "01". The higher-order bits of the instruction register can receive any design specific values. The Capture-IR state is used for testing the instruction register. Faults in the instruction register, if any exist, may be detected by shifting out the data loaded in it. When the controller is in this state, it moves to either the Shift-IR state if TMS is low, or the Exit1-IR state if TMS is high. * Shift-IR In this state, the instruction register is connected between TDI and TDO and shifts the captured data toward its serial output on the rising edge of TCK. When the controller is in this state, it remains in the Shift-IR state if TMS is low, or moves to the Exit1-IR state if TMS is high. TMP1962-390 2006-02-21 TMP1962C10BXBG * Exit 1-IR This is a temporary controller state. When the controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. * Pause-IR This state allows the shifting of the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the controller is in this state, it remains in the Pause-IR state if TMS is held low, or moves to the Exit2-IR state if TMS is held high. * Exit 2-IR This is a temporary controller state. When the controller is in this state, it moves to either the Shift-IR state if TMS is held low, or the Update-IR state if TMS is held high. * Update-IR This state allows the instruction previously shifted into the instruction register to be output in parallel on the rising edge of TCK. Then it becomes the current instruction, setting a new operational mode. When the controller is in this state, it moves to either the Run-Test/Idle state if TMS is low, or the Select-DR-Scan state if TMS is high. TMP1962-391 2006-02-21 TMP1962C10BXBG Table 21.2 shows the boundary scan order of the processor signals. Table 21.2 TMP1962 JTAG Boundary-Scan Ordering [TDI] 7: 14: 21: 28: 35: 42: 49: 56: 63: 70: 77: 84: 91: 98: PCST2 SYSRDY BW1 PN1 PP6 PP2 PB0 PA7 PA6 PF6 PG2 PD0 PH1 PH2 1: 8: 15: 22: 29: 36: 43: 50: 57: 64: 71: 78: 85: 92: 99: PJ4 PJ1 PN7 PO5 PO0 PO7 PB1 PA3 PA5 PG0 PD6 PD4 PC3 PC5 2: 16: 23: 30: 37: 44: 51: 58: 65: 72: 79: 86: 93: PJ2 BW0 DRESET 3: 10: 17: 24: 31: 38: 45: 52: 59: 66: 73: 80: 87: 94: PCST3 DBGE 4: 11: 18: 25: 32: 39: 46: 53: 60: 67: 74: 81: 88: 95: PSCT0 DCLK RESET 5: 12: 19: 26: 33: 40: 47: 54: 61: 68: 75: 82: 89: 96: PJ3 PJ0 PLLOFF 6: 13: 20: 27: 34: 41: 48: 55: 62: 69: 76: 83: 90: 97: SDI/ DINT PCST1 NMI SDAO/TPC 9: TEST5 PN6 PO6 PP7 PP0 PB4 PF4 PF2 PD7 PD1 PC6 PC4 PN2 PN0 PP5 PP4 PB6 PA0 PF7 PF5 PD3 PC2 PH0 PN5 PO3 PO4 PB2 PA1 PA2 PF1 PG3 PD2 PC1 PH5 PN3 PO2 PP3 PB3 PA4 PB5 PF0 PG1 PG6 PC0 PH4 PN4 PO1 PP1 PB7 PF3 PG5 PG7 PG4 PD5 PC7 PH3 100: PE2 107: PE4 114: P50 121: P66 128: P61 135: P00 142: P11 149: P36 156: P16 163: P42 170: PI3 177: PK1 184: PM6 191: PL5 198: P77 205: P83 212: P97 219: P92 101: PE0 108: RSTPUP 115: P52 122: P55 129: P21 136: P27 143: P10 150: P17 157: P41 164: PK5 171: PM7 178: PK4 185: PM3 192: PL4 199: P73 206: P85 213: P93 [TDO]: 102: PE1 109: PE6 116: P64 123: P51 130: P22 137: P01 144: P07 151: P34 158: P35 165: PI7 172: PK6 179: PK2 186: PM0 193: PL0 200: P70 207: P76 214: P94 103: PH7 110: PE7 117: P63 124: P26 131: P02 138: P06 145: P12 152: P40 159: P44 166: PI6 173: PI1 180: PL7 187: PM1 194: PL3 201: P71 208: P82 215: P96 104: PH6 111: P53 118: P56 125: P65 132: P23 139: P03 146: P15 153: P32 160: P37 167: PK7 174: PI2 181: PM5 188: PM2 195: PL1 202: P72 209: P80 216: P90 105: PE5 112: P60 119: P67 126: P20 133: P25 140: P05 147: P13 154: P33 161: P31 168: PI5 175: PI0 182: PK0 189: PL6 196: P75 203: P86 210: P81 217: P95 106: PE3 113: P57 120: P62 127: P54 134: P24 141: P04 148: P14 155: P30 162: P43 169: PI4 176: PK3 183: PM4 190: PL2 197: P74 204: P84 211: P87 218: P91 TMP1962-392 2006-02-21 TMP1962C10BXBG 21.4 Instructions for JTAG This section defines the instructions supplied and the operations that occur in response to those instructions. 21.4.1 The EXTEST Instruction This instruction is used for external interconnect test, and targets the boundary scan register between TDI and TDO. The EXTEST instruction permits BSR cells at output pins to shift out test patterns in the Update-DR state and those at input pins to capture test results in the Capture-DR state. Typically, before EXTEST is executed, the initialization pattern is first shifted into the boundary scan register using the SAMPLE/PRELOAD instruction. In the Update-DR state, the boundary scan register loaded with the initialization pattern causes known data to be driven immediately from the IC onto its external interconnects. This eliminates the possibility of bus conflicts damaging the IC outputs. The flow of data through the boundary scan register while the EXTEST instruction is selected is shown in Figure 21.8, which follows: Boundary Scan Path INPUT Core Logic OUTPUT TDI TDO Figure 21.8 Test Data Flow While the EXTEST Instruction is Selected The following steps describe the basic test algorithm of an external interconnect test. 1. Initialize the TAP controller to the Test-Logic-Reset state. 2. Load the instruction register with SAMPLE/PRELOAD. This causes the boundary scan register to be connected between TDI and TDO. 3. Initialize the boundary scan register by shifting in determinate data. 4. Then, load the initial test data into the boundary scan register. 5. Load the instruction register with EXTEST. 6. Capture the data applied to the input pin into the boundary scan register. 7. Shift out the captured data while simultaneously shifting in the next test pattern. 8. Read out the data in the boundary scan register onto the output pin. Steps 6 to 8 are repeated for each test pattern. TMP1962-393 2006-02-21 TMP1962C10BXBG 21.4.2 The SAMPLE/PRELOAD Instruction This instruction targets the boundary scan register between TDI and TDO. As the instruction's name implies, two functions are performed through use of the SAMPLE/ PRELOAD instruction. * SAMPLE allows the input and output pads of an IC to be monitored. While it does so, it does not disconnect the system logic from the IC pins. The SAMPLE function occurs in the Capture-DR controller state. An example application of SAMPLE is to take a snapshot of the activity of the IC's I/O pins so as to verify the interaction between ICs during normal functional operation. The flow of data for the SAMPLE phase of the SAMPLE/PRELOAD instruction is shown in Figure 21.9. Boundary Scan Path INPUT Core Logic OUTPUT TDI TDO Figure 21.9 Test Data Flow While SAMPLE is Selected * PRELOAD allows the boundary scan register to be initialized before another instruction is selected. For example, prior to selection of the EXTEST instruction, initialization data is shifted into the boundary scan register using PRELOAD as described in the previous subsection. PRELOAD permits shifting of the boundary scan register without interfering with the normal operation of the system logic. The flow of data for the PRELOAD phase of the SAMPLE/PRELOAD instruction is shown in Figure 21.10. Boundary Scan Path INPUT Core Logic OUTPUT TDI TDO Figure 21.10 Test Data Flow While PRELOAD is Selected TMP1962-394 2006-02-21 TMP1962C10BXBG 21.4.3 The BYPASS Instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides a minimum length serial path through the IC (or between JTDI and JTDO) when the IC is not required for the current test. The BYPASS instruction does not cause interference to the normal operation of the on-chip system logic. The flow of data through the bypass register while the BYPASS instruction is selected is shown in Figure 21.11. Bypass Register TDI 1-bit TDO Figure 21.11 Test Data Flow While the Bypass Instruction is Selected 21.5 Note This section describes details of JTAG boundary-scan operation that are specific to the processor. * * The X2, and X1 signal pads do not support JTAG. When performing a JTAG operation, be sure to run the MasterClock before and after a reset operation to properly release the processor reset. * Reset for JTAG (1) JTAG circuit is initialized by TRST assertion. And then deassert TRST . (2) At input to TMS = 1 and asserted for more 5 TCK cycles. TMP1962-395 2006-02-21 TMP1962C10BXBG 22. Electrical Characteristics The letter x in equations presented in this chapter represents the cycle period of the fsys clock selected through the programming of the SYSCR1.SYSCK bit. The fsys clock may be derived from either the high-speed or low-speed crystal oscillator. The programming of the clock gear function also affects the fsys frequency. All relevant values in this chapter are calculated with the high-speed (fc) system clock (SYSCR1.SYSCK = 0) and a clock gear factor of 1/fc (SYSCR1.GEAR[1:0] = 00). 22.1 Absolute Maximum Ratings Parameter Symbol VCC15 (Core) Supply voltage VCC2 (I/O) VCC3 (I/O) AVCC (A/D) Input voltage Low-level output current High-level output current Per pin Total Per pin Total VIN IOL IOL IOH IOH PD TSOLDER TSTG TOPR Rating -0.3 to 3.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 3.6 -0.3 to VCC + 0.3 5 50 -5 50 600 260 -65 to 150 -20 to 85 Unit V V mA Power dissipation (Ta = 85C) Soldering temperature (10 s) Storage temperature Operating temperature mW C C C VCC15 = DVCC15 = CVCC15, VCC2 = DVCC2, VCC3 = DVCC3n (n = 1 to 4), AVCC = AVCC3m (m = 1 to 2), VSS = DVSS* = AVSS* = CVSS Note: Absolute Maximum Ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no Absolute Maximum Ratings value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. TMP1962-396 2006-02-21 TMP1962C10BXBG 22.2 DC Electrical Characteristics (1/4) Ta = -20 to 85C Parameter Symbol DVCC15 DVCC2 DVCC3n (n = 1 to 4) Conditions fosc = 10 to 13.5 MHz fsys = 3.75 to 40.5 MHz PLLON, INTLV = "H" fsys = 3 to 40.5 MHz fsys = 3 to 40.5 MHz 2.7 V AVCC32 AVCC31 3.3 V 1.65 AVCC32 AVCC31 < 2.7 V 1.65 V DVCC3n 3.3 V (n = 1 to 4) Min 1.35 2.3 1.65 Typ (Note 1) Max 1.65 3.3 3.3 0.3 AVCC31 0.3 AVCC32 Unit Supply voltage CVCC15 = DVCC15 CVSS = DVSS = 0 V V P7-P9 (Used as a port) P0-P6, PA-PC, PD0-PD6, Low-level input voltage PE0-PE2, PF2-PF7, PG-PH, PI7, PJ1-PJ4, PL-PP PD7, PE3-PE7, PF0-PF1, PI0-PI6, PJ0, PK, PLLOFF , RSTPUP, RESET DRESET , DBGE VIL1 VIL2 0.3 DVCC3n 2.3 V DVCC2 3.3 V 0.3 DVCC2 2.7 V DVCC3n 3.3 V (n = 1 to 4) 2.7 V DVCC2 3.3 V -0.3 0.15 DVCC3n V VIL3 1.65 V DVCC3n < 2.7 V (n = 1 to 4) 2.3 V DVCC2 < 2.7 V 0.1 DVCC3n 0.1 DVCC2 SDI/ DINT , TCK, TMS, TDI, TRST NMI , BW0, BW1 X1 VIL4 1.35 V CVCC15 1.65 V 0.1 CVCC15 Note 1: Ta = 25C, DVCC3 = 3.0 V, DVCC2 = 2.5 V, AVCC3 = 3.3 V, unless otherwise noted. TMP1962-397 2006-02-21 TMP1962C10BXBG 22.3 DC Electrical Characteristics (2/4) Ta = -20 to 85C Parameter P7-P9 (Used as a port) P0-P6, PA-PC, PD0-PD6, High-level input voltage PE0-PE2, PF2-PF7, PG-PH, PI7, PJ1-PJ4, PL-PP PD7, PE3-PE7, PF0-PF1, PI0-PI6, PJ0, PK, PLLOFF , RSTPUP, RESET DRESET , DBGE Symbol Conditions 2.7 V AVCC32 AVCC31 3.3 V Min 0.7 AVCC31 0.7 AVCC32 Typ. (Note 1) Max Unit VIH1 1.65 AVCC32 AVCC31 < 2.7 V 1.65 V DVCC3n 3.3 V (n = 1 to 4) VIH2 2.3 V DVCC2 3.3 V 0.7 DVCC3n 0.7 DVCC2 DVCC3n + 0.3 DVCC2 + 0.3 0.85 DVCC3n CVCC15 + 0.2 2.7 V DVCC3n 3.3 V (n = 1 to 4) 2.7 V DVCC2 3.3 V VIH3 1.65 V DVCC3n < 2.7 V (n = 1 to 4) 2.3 V DVCC2 < 2.7 V V SDI/ DINT , TCK, TMS, TDI, TRST NMI , BW0, BW1 0.9 DVCC3n 0.9 DVCC2 X1 VIH4 1.35 V CVCC15 1.65 V DVCC3n 2.7 V DVCC2 2.7 V DVCC3n < 2.7 V DVCC2 < 2.7 V DVCC3n 2.7 V DVCC2 2.7 V DVCC3n < 2.7 V DVCC2 < 2.7 V 0.9 CVCC15 IOL = 2 mA Low-level output voltage VOL IOL = 500 A 0.4 0.2 DVCC3n 0.4 0.2 DVCC2 0.4 V IOH = -2 mA High-level output voltage VOH IOH = -500 A 2.4 0.8 DVCC3n 0.8 DVCC2 Note 1: Ta = 25C, DVCC3 = 3.0 V, DVCC2 = 2.5 V, AVCC3 = 3.3 V, unless otherwise noted. TMP1962-398 2006-02-21 TMP1962C10BXBG 22.4 DC Electrical Characteristics (3/4) Ta = -20 to 85C Parameter Symbol Conditions 0.0 VIN DVCC2 0.0 VIN DVCC3n (n = 1 to 4) 0.0 VIN AVCC31 0.0 VIN AVCC32 0.2 VIN DVCC2 - 0.2 Min Typ. (Note 1) Max Unit Input leakage current ILI 0.02 5 A Output leakage current ILO 0.2 VIN DVCC3n - 0.2 (n = 1 to 4) 0.2 VIN AVCC31 - 0.2 0.2 VIN AVCC32 - 0.2 0.05 10 VSTOP (DVCC15) VSTOP1 (DVCC2) Power-down voltage (STOP mode RAM backup) VSTOP2 (DVCC3) (AVCC3) VIL2 = 0.2DVCC2, VIL3 = 0.1DVCC2 VIH2 = 0.8DVCC2, VIH3 = 0.9DVCC2 VIL = 0.3DVCC33, VIL1 = 0.3AVCC31,32 VIL2 = 0.3DVCC3n, VIL3 = 0.1DVCC3n VIH = 0.7DVCC33, VIH1 = 0.7AVCC31,32 VIH2 = 0.7DVCC3n, VIH3 = 0.9DVCC3n (n = 1 to 4) Pull-up resistor at Reset Schmitt width PD7, PE3-PE7, PF0-PF1, PI0-PI6, PJ0, PK, PLLOFF , RSTPUP, RESET , DRESET , DBGE , SDI/ DINT , TCK, TMS, TDI, TRST , NMI , BW0, BW1 Programmable pull-up/ pull-down resistor P32-P37,P40-P43 KEY0-KEYD, DRESET, DBGE , SDI/ DINT , TCK, TMS, 1.35 2.3 1.65 3.3 V 1.65 3.3 RRST DVCC2 = 2.5 V 0.2 V 2.7 V DVCC3n 3.3 V (n = 2, 4) 2.7 V DVCC2 3.3 V 20 50 240 k 0.4 0.9 V VTH 1.65 V DVCC3n < 2.7 V (n = 2, 4) 2.3 V DVCC2 < 2.7 V DVCC3n = 3.0 V 0.3 V (n = 2 to 4) PKH DVCC3n = 2.5 V 0.2 V (n = 2 to 4) DVCC2 = 2.5 V 0.2 V DVCC3n = 2.0 V 0.2 V (n = 2 to 4) DVCC2 = 2.0 V 0.2 V CIO fc = 1 MHz 0.3 0.6 15 20 25 50 50 160 100 240 600 10 pF k TDI, TRST Pin capacitance (Except power supply pins) Note 1: Ta = 25C, DVCC3n = 3.0 V, DVCC2 = 2.5 V, AVCC3 = 3.0 V, unless otherwise noted. TMP1962-399 2006-02-21 TMP1962C10BXBG 22.5 DC Electrical Characteristics (4/4) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, DVCC3n = 3.0 V 0.3 V, AVCC3m = 3.3 V 0.2 V Ta = 20 to 85C (n = 1 to 4, m = 1, 2) Parameter NORMAL (Note 2): Gear = 1/1 IDLE (Doze) IDLE (Halt) Symbol Conditions fsys = 40.5 MHz (fOSC = 13.5 MHz, PLLON) INTLV = "H" Min Typ. (Note 1) 38 16 13 Max 46 28 23 Unit mA ICC DVCC15 = CVCC15 = 1.35 to 1.65 V DVCC2 = 2.3 to 2.7 V DVCC3n = 1.65 to 3.3 V AVCC3m = 3.7 to 3.3 V 50 900 A STOP Note 1: Ta = 25C, DVCC15 = 1.5 V, DVCC2 = 2.5 V, DVCC3n = 3.0 V, AVCC3m = 3.0 V, unless otherwise noted. Note 2: Measured with the CPU drystone operating, all I/O peripherals channel on, and 16-bit external bus operated with 4 system clocks. Note 3: The supply current flowing through the DVCC15, DVCC2, DVCC3n, CVCC15 and AVCC3m pins is included in the digital supply current parameter (ICC). TMP1962-400 2006-02-21 TMP1962C10BXBG 22.6 10-bit ADC Electrical Characteristics DVCC15= CVCC15= 1.5 0.15 V, DVCC2 = 2.5 0.2 V, DVCC3n = 3.0 0.3 V, AVCC3m = 3.0 0.3 V, AVSS = DVSS, Ta = -20 to 85C Parameter Analog reference voltage (+) Analog reference voltage (-) Analog input voltage A/D conversion IREF Non-A/D conversion AVCCm INL error = VREFH = 3.0 V 0.3 V DVSS = AVSS = VREFL DNL error AIN resistance < 13.3 k AIN load capacitance < 20 pF AVCCm load capacitance 10 F Offset error VREFH load capacitance 10 F Conversion time 7.9 s Note* Gain error 2 6 LSB 2 3 LSB 1.5 3 LSB 2 3 LSB Symbol VREFH VREFL VAIN AVCCm Conditions Min 2.7 AVCCm - 0.3 AVSS VREFL Typ. (Note 1) AVCC AVSS Max 3.3 AVCCm + 0.3 AVSS + 0.2 VREFH Unit V V V mA = VREFH = 3.0 V 0.3 V DVSS = AVSS = VREFL AVCCm = VREFH = 3.0 V 0.3 V DVSS = AVSS = VREFL 0.35 1.0 Analog supply current 0.02 10 A Analog input capacitance Analog input impedance 5.0 5.0 pF k Note 1: 1LSB = (VREFH - VREFL)/1024[V] Note 2: The supply current flowing through the AVCCm pin is included in the digital supply current parameter (ICC). Note*:Connection of an external capacitor is recommended* 0.1 F TMP1962-401 2006-02-21 TMP1962C10BXBG AC Electrical Characteristics 22.6.1 Multiplex Bus Mode (1) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.0 0.3 V, DVCC33 = 3.0 V 0.3 V, Ta = -20 to 85C 1. ALE width = 0.5 clock cycle, 1 programmed wait state Equation Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high No. Parameter Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW 24.6 40.5 MHz (fsys) (Note) Max Min 8 10.5 12 10 24 19.5 19.5 23 Unit ns ns ns ns ns ns ns ns ns Max 0.5x - 4.3 0.5x - 1.8 0.5x - 0.3 0.5x - 2.3 x - 0.6 x - 5.1 x - 5.1 x - 1.6 x (2 + W) - 35.8 x (2 + W) - 35.8 x (1 + W) - 30.7 x (1 + W) - 2.7 0 x - 0.1 x (1 + W) - 3.2 x (1 + W) - 4.2 x - 0.1 x (3 + 0.5) - 21.6 x (3 + 0.5) - 21.6 x (0.5 + 3 + N - 2) - 4.1 x (1.5 + 3 + N -2) - 18.7 A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low 38 38 18.5 46.5 0 24.5 46 45 24.5 64.5 64.5 57.4 67.4 ns ns ns ns ns ns ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-402 2006-02-21 TMP1962C10BXBG 2. ALE width = 1.5 clock cycles, 1 programmed wait state Equation Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high No. Parameter Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW 24.6 40.5 MHz (fsys) (Note) Max Min 33 10.5 36.5 10 24 44 44 23 Unit ns ns ns ns ns ns ns ns ns Max 1.5x - 3.9 0.5x - 1.8 1.5x - 0.4 0.5x - 2.4 x - 0.6 2x - 5.2 2x - 5.2 x - 1.6 x (3 + W) - 35.9 x (3 + W) - 35.9 x (1 + W) - 30.7 x (1 + W) - 2.7 0 x x (1 + W) - 3.2 x (1 + W) - 4.2 x - 0.1 x (4 + 0.5) - 21.7 x (4 + 0.5) - 21.7 x (0.5 + 3 + N - 2) - 4.1 x (1.5 + 3 + N - 2) - 18.7 A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low 62.5 62.5 18.5 46.5 0 24.6 46 45 24.5 89 89 57.4 67.4 ns ns ns ns ns ns ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-403 2006-02-21 TMP1962C10BXBG (2) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.3 0.2 V, DVCC33 = 2.5 V 0.2 V, Ta = -20 to 85C 1. ALE width = 0.5 clock cycle, 1 programmed wait state Equation Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high No. Parameter Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW 24.6 40.5 MHz (fsys) (Note) Max Min 10 10.5 12 10 24 19.5 19.5 23 Unit ns ns ns ns ns ns ns ns ns Max 0.5x - 2.3 0.5x - 1.8 0.5x - 0.3 0.5x - 2.3 x - 0.6 x - 5.1 x - 5.1 x - 1.6 x (2 + W) - 36.8 x (2 + W) - 36.8 x (1 + W) - 31.7 x (1 + W) - 2.2 0 x - 0.1 x (1 + W) - 2.7 x (1 + W) - 3.8 x -0.1 x (3 + 0.5) - 22.6 x (3 + 0.5) - 22.6 x (0.5 + 3 + N - 2) - 5.1 x (1.5 + 3 + N - 2) - 19.7 A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low 37 37 17.5 47 0 24.5 46.5 45.5 24.5 63.5 63.5 56.4 66.4 ns ns ns ns ns ns ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-404 2006-02-21 TMP1962C10BXBG 2. ALE width = 1.5 clock cycles, 1 programmed wait state Equation Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high No. Parameter Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW 24.6 40.5 MHz (fsys) (Note) Max Min 34.5 10.5 36.5 10 24 44 44 23 Unit ns ns ns ns ns ns ns ns ns Max 1.5x - 2.4 0.5x - 1.8 1.5x - 0.4 0.5x - 2.4 x - 0.6 2x - 5.2 2x - 5.2 x - 1.6 x (3 + W) - 36.9 x (3 + W) - 36.9 x (1 + W) - 31.7 x (1 + W) - 2.2 0 x - 0.1 x (1 + W) - 2.7 x (1 + W) - 3.8 x -0.1 x (4 + 0.5) - 22.6 x (4 + 0.5) - 22.6 x (0.5 + 3 + N - 2) - 5.1 x (1.5 + 3 + N - 2) - 19.7 A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low 61.5 61.5 17.5 47 0 24.5 46.5 45.5 24.5 88.1 88.1 56.4 66.4 ns ns ns ns ns ns ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-405 2006-02-21 TMP1962C10BXBG (3) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.3 0.2 V, DVCC33 = 1.8 V 0.15 V, Ta = -20 to 85C 1. ALE width = 0.5 clock cycle, 2 programmed wait state Equation Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high No. Parameter Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW 24.6 40.5 MHz (fsys) (Note) Max 33333 10 10.5 12 10 24 19.5 19.5 23 Unit ns ns ns ns ns ns ns ns ns Min Max 0.5x - 2.3 0.5x - 1.8 0.5x - 0.3 0.5x - 2.3 x - 0.6 x - 5.1 x - 5.1 x - 1.6 x (2 + W) - 42.4 x (2 + W) - 42.4 x (1 + W) - 37.3 x (1 + W) - 2.3 0 x - 0.1 x (1 + W) - 2.8 x (1 + W) - 3.8 x - 0.1 x (3 + 0.5) - 28.1 x (3 + 0.5) - 28.1 x (0.5 + 3 + N - 2) - 6.1 x (1.5 + 3 + N - 2) - 24.7 A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low 56 56 36.5 71.5 0 24.5 71 70 24.5 58 58 55.4 61.4 ns ns ns ns ns ns ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-406 2006-02-21 TMP1962C10BXBG 2. ALE width = 1.5 clock cycles, 2 programmed wait states Equation No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Parameter System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD , WR or HWR asserted RD , WR or HWR negated to ALE high Symbol Min tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW x (0.5 + 3 + N - 1) - 6.1 x (1 + W) - 2.3 0 x - 0.1 x (1 + W) - 2.8 x (1 + W) - 3.8 x - 0.1 x (4 + 0.5) - 28.1 x (4 + 0.5) - 28.1 x (1.5 + 3 + N - 1) - 24.7 24.6 1.5x - 2.4 0.5x - 1.8 1.5x - 0.4 0.5x - 2.3 x - 0.6 2x - 5.2 2x - 5.2 x - 1.6 x (3 + W) - 42.5 x (3 + W) - 42.5 x (1 + W) - 37.3 40.5 MHz (fsys) (Note) Max Min 34.5 10.5 36.5 10 24 44 44 23 80.5 80.5 36.5 71.5 0 24.5 71 70 24.5 82.6 82.6 80 86 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max A0-A15 valid to RD , WR or HWR asserted A16-A23 valid to RD , WR or HWR asserted A16-A23 hold after RD , WR or HWR negated A0-A15 valid to D0-D15 Data in A16-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low D0-D15 hold after RD negated RD negated to next A0-A15 output WR or HWR width low D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A16-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD , WR or HWR asserted Note: Nos. 1 to 18 indicate the values obtained with 1 programmed wait state. Nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-407 2006-02-21 TMP1962C10BXBG (1) Read cycle timing, ALE width = 0.5 clock cycle, 1 programmed wait state BUS Cycle = 4 CLK Cycles Internal CLK S1 tLL W1 S2 S3 S1 ALE tAL tCL tLA AD0 to AD15 A0 to A15 tADL tADH A16 to A23 tACH tACL tLC tRD tRR tCAR tRAE tHR D0 to D15 RD CS0 to CS3 R/W TMP1962-408 2006-02-21 TMP1962C10BXBG (2) Read cycle timing, ALE width = 1.5 clock cycles, 1 programmed wait state BUS Cycle = 5 CLK Cycles Internal CLK S0 tLL S1 W1 S2 S3 S0 ALE tAL tCL tLA AD0 to AD15 A0 to A15 tADL tADH A16 to A23 tACH tACL tLC tRR tRD tCAR tRAE tHR D0 to D15 RD CS0 to CS3 R/W TMP1962-409 2006-02-21 TMP1962C10BXBG (3) Read cycle timing, ALE width = 1.5 clock cycles, 2 externally generated wait states with N = 1 BUS Cycle = 6 CLK Cycles Internal CLK S1 W W S2 S3 S0 ALE AD0 to AD15 A0 to A15 D0 to D15 AD16 to AD23 RD tCW CS0 to CS3 R/W tAWL/H WAIT TMP1962-410 2006-02-21 TMP1962C10BXBG (4) Read cycle timing, ALE width = 1.5 clock cycles, 4 externally generated wait states with N=1 BUS Cycle = 8 CLK Cycles Internal CLK S1 W W W W S2 S3 S0 ALE AD0 to AD15 A0 to A15 D0 to D15 AD16 to AD23 RD tCW CS0 to CS3 R/W tAWL/H WAIT TMP1962-411 2006-02-21 TMP1962C10BXBG (5) Write cycle timing, ALE width = 1.5 clock cycles, zero wait state BUS Cycle = 4 CLK Cycles Internal CLK tLL ALE tAL tCL tLA AD0 to AD15 A0 to A15 D0 to D15 tDW AD16 to AD23 tACH tACL tLC tWW tCAR tWD WR , HWR CS0 to CS3 R/W TMP1962-412 2006-02-21 TMP1962C10BXBG 22.6.2 Separate Bus Mode (1) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.3 0.2 V, DVCC33 = 3.0 V 0.3 V, Ta = -20 to 85C 1. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAW tCW 24.6 x - 5.1 x - 1.6 40.5 MHz (fsys) (Note) Max Min 19.5 23 Unit ns ns ns Max x (2 + W) - 35.8 x (1 + W) - 30.7 x (1 + W) - 2.7 0 x- 0.1 x (1 + W) - 3.2 x (1 + W) - 4.2 x - 0.1 x (3 + 0.5) - 21.6 x (0.5 + 3 + N - 2) - 4.1 x (1.5 + 3 + N - 2) - 18.7 57.4 45 24.5 46.5 0 24.5 46 38 18.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 1 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR 64.5 67.4 ns ns asserted Note: Nos. 1 to 12 indicate the values obtained with 1 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-413 2006-02-21 TMP1962C10BXBG 2. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAW tCW 24.6 2x - 5.2 x - 1.6 40.5 MHz (fsys) (Note) Max Min 44 23 Unit ns ns ns Max x (3 + W) - 35.9 x (1 + W) - 30.7 x (1 + W) - 2.7 0 x x (1 + W) - 3.2 x (1 + W) - 4.2 x - 0.1 x (4 + 0.5) - 21.7 x (0.5 + 3 + N - 2) - 4.1 x (1.5 + 3 + N - 2) - 18.7 57.4 45 24.5 46.5 0 24.6 46 62.5 18.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 1 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR asserted 89 67.4 ns ns Note: Nos. 1 to 12 indicate the values obtained with 1 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-414 2006-02-21 TMP1962C10BXBG (2) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.3 0.2 V, DVCC33 = 2.5 V 0.2 V, Ta = -20 to 85C 1. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAW tCW 24.6 x - 5.1 x - 1.6 40.5 MHz (fsys) (Note) Max Min 19.5 23 Unit ns ns ns Max x (2 + W) - 36.8 x (1 + W) - 31.7 x (1 + W) - 2.2 0 x - 0.1 x (1 + W) - 2.7 x (1 + W) - 3.8 x -0.1 x (3 + 0.5) - 22.6 x (0.5 + 3 + N - 2) - 5.1 x (1.5 + 3 + N - 2) - 19.7 56.4 45.5 24.5 47 0 24.5 46.5 37 17.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 1.5 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR 63.5 66.4 ns ns asserted Note: Nos. 1 to 12 indicate the values obtained with 1 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-415 2006-02-21 TMP1962C10BXBG 2. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAW tCW 24.6 2x - 5.2 x - 1.6 40.5 MHz (fsys) (Note) Max Min 44 23 Unit ns ns ns Max x (3 + W) - 36.9 x (1 + W) - 31.7 x (1 + W) - 2.2 0 x - 0.1 x (1 + W) - 2.7 x (1 + W) - 3.8 x -0.1 x (4 + 0.5) - 22.6 x (0.5 + 3 + N - 2) - 5.1 x (1.5 + 3 + N - 2) - 19.7 56.4 45.5 24.5 47 0 24.5 46.5 61.5 17.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 1.5 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR asserted 88.1 66.4 ns ns Note: Nos. 1 to 12 indicate the values obtained with 1 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-416 2006-02-21 TMP1962C10BXBG (3) DVCC15 = CVCC15 = 1.5 V 0.15 V, DVCC2 = 2.5 V 0.2 V, AVCC3m = 3.3 0.2 V, DVCC33 = 1.8 V 0.15 V, Ta = -20 to 85C 1. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAWH tCW 24.6 x - 5.1 x - 1.6 40.5 MHz (fsys) (Note) Max Min 19.5 23 Unit ns ns ns Max x (2 + W) - 42.4 x (1 + W) - 37.3 x (1 + W) - 2.3 0 x - 0.1 x (1 + W) - 2.8 x (1 + W) - 3.8 x - 0.1 x (3 + 0.5) - 28.1 x (0.5 + 3 + N - 2) - 6.1 x (1.5 + 3 + N -2) - 24.7 55.4 70 24.5 71.5 0 24.5 71 56 36.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 2 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR 58 61.4 ns ns asserted Note: Nos. 1 to 12 indicate the values obtained with 2 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-417 2006-02-21 TMP1962C10BXBG 2. SYSCR3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 System clock period (x) A0-A23 valid to RD , WR or HWR asserted A0-A23 hold after RD , WR or HWR negated A0-A23 valid to D0-D15 Data in RD asserted to D0-D15 data in RD width low No. Parameter Symbol tSYS tAC tCAR tAD tRD tRR tHR tRAE tWW tDO tDW tWD tAWH tCW 24.6 2x - 5.2 x - 1.6 40.5 MHz (fsys) (Note) Max Min 44 23 Unit ns ns ns Max x (3 + W) - 42.5 x (1 + W) - 37.3 x (1 + W) - 2.3 0 x - 0.1 x (1 + W) - 2.8 x (1 + W) - 3.8 x - 0.1 x (4 + 0.5) - 28.1 x (0.5 + 3 + N - 2) - 6.1 x (1.5 + 3 + N - 2) - 24.7 55.4 70 24.5 71.5 0 24.5 71 80.5 36.5 ns ns ns ns ns ns D0-D15 hold after RD negated RD negated to next A0-A23 output WR or HWR width low WR or HWR asserted to D0-D15 valid 2 ns ns ns D0-D15 valid to WR or HWR negated D0-D15 hold after WR or HWR negated A0-A23 valid to WAIT input WAIT hold after RD , WR or HWR asserted 82.6 61.4 ns ns Note: Nos. 1 to 12 indicate the values obtained with 2 programmed wait state. Nos. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: * * Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962-418 2006-02-21 TMP1962C10BXBG (1) Read cycle timing (SYSCR3 BUS Cycle = 4 CLK Cycles Internal CLK S1 W1 S2 S3 S1 CS0 to CS3 tAD tAC tHR D0 to D15 A0 to A23 D0 to D15 tRR tRD RD tCAR tRAE R/W TMP1962-419 2006-02-21 TMP1962C10BXBG (2) Read cycle timing (SYSCR3 BUS Cycle = 5 CLK Cycles Internal CLK S0 S1 W1 S2 S3 S0 CS0 to CS3 tAD A16 to A23 tAC tAD D0 to D15 tHR D0 to D15 tRR tRD tCAR tRAE RD R/W TMP1962-420 2006-02-21 TMP1962C10BXBG (3) Read cycle timing SYSCR3 BUS Cycle = 6 CLK Cycles Internal CLK S1 W W S2 S3 S0 CS0 to CS3 A0 to A23 D0 to D15 D0 to D15 RD tCW R/W tAW WAIT TMP1962-421 2006-02-21 TMP1962C10BXBG (4) Read cycle timing (SYSCR3 BUS Cycle = 8 CLK Cycles Internal CLK S1 W W W W S2 S3 S0 CS0 to CS3 A0 to A23 D0 to D15 D0 to D15 RD tCW R/W tAW WAIT TMP1962-422 2006-02-21 TMP1962C10BXBG (5) Write cycle timing (SYSCR3 BUS Cycle = 4 CLK Cycles Internal CLK CS0 to CS3 A0 to A23 tAC tDW D0 to D15 tDO tWW D0 to D15 tWD tCAR WR , HWR R/W TMP1962-423 2006-02-21 TMP1962C10BXBG 22.7 Transfer with DMA Request The following shows an example of a transfer between the on-chip RAM and an external device in multiplex bus mode. * * * * 16-bit data bus width, non-recovery time Level data transfer mode Transfer size of 16 bits, device port size (DPS) of 16 bit Source/destination: on-chip RAM/external device The following shows transfer operation timing of the on-chip RAM to an external bus during write operation (memory-to-memory transfer). (2) (1) DREQn ALE A [23:16] AD [15:0] (N - 2)th transfer RD (N - 1)th transfer Nth transfer WR HWR CSn R/W (1) Indicates the condition under which Nth transfer is performed successfully. (2) Indicates the condition under which (N + 1)th transfer is not performed. TMP1962-424 2006-02-21 TMP1962C10BXBG (1) DVCC2m = FVCC2 = CVCC2 = 2.5 V 0.2 V, FVCC3 = 3.3 V 0.3 V, AVCC3m = 3.3 0.2 V, DVCC33 = 2.3 V to 3.3 V, Ta = 20 to 85C (m = 1 to 2) 40.5 MHz (fsys) (Note) Min 45 0 No. Parameter RD asserted to DREQn asserted Symbol (1) Min Equation (2) Max (2W + ALE + 6) x - 51 (2W + ALE + 4) x - 51.8 Unit Max 195 145 ns ns 2 3 (external device to on-chip RAM transfer) WR / HWR asserted to DREQn asserted (on-chip RAM to external device transfer) tDREQ_r tDREQ_w Wx - 4.2 0 (2) DVCC2m = FVCC2 = CVCC2 = 2.5 V 0.2 V, FVCC3 = 3.3 V 0.3 V, AVCC3m = 3.3 0.2 V, DVCC33 = 1.8 V 0.15 V, Ta = 20 to 85C (m = 1 to 2) 40.5 MHz (fsys) (Note) Min 43 0 No. Parameter RD asserted to DREQn asserted Symbol (1) Min Equation (2) Max (2W + ALE + 6) x - 56 (2W + ALE + 4) x - 56.8 Unit Max 190 140 ns ns 2 3 (external device to on-chip RAM transfer) WR / HWR asserted to DREQn asserted (on-chip RAM to external device transfer) tDREQ_r tDREQ_w Wx - 6.2 0 W: Number of wait-state cycles inserted. In the case of (1 + N) externally generated wait states with N = 1, W becomes 2. ALE: Apply ALE = 0 for ALE 0.5 clock, ALE = 1 for ALE 1.5 clock. The values in the above table are obtained with W = 2, ALE = 0. TMP1962-425 2006-02-21 TMP1962C10BXBG 22.8 Serial Channel Timing (1) I/O Interface Mode (DVCC3n = 3.0 V 0.3V) In the table below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. 1. SCLK input mode (SIO0 to SIO6) Parameter SCLK period TxD data to SCLK rise of fall* TxD data hold after SCLK rise or fall* RxD data valid to SCLK rise or fall* RxD data hold after SCLK rise or fall* Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 12x 2x - 45 8x - 15 30 2x - 30 40.5 MHz Min 296 4 182 30 19 Max Max Unit ns ns ns ns ns * SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 2. SCLK output mode (SIO0 to SIO6) Parameter SCLK period (programmable) TxD data to SCLK rise TxD data hold after SCLK rise RxD data valid to SCLK rise RxD data hold after SCLK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 8x 4x - 10 4x - 10 45 0 40.5 MHz Min 197 88 88 45 0 Max Max Unit ns ns ns ns ns TMP1962-426 2006-02-21 TMP1962C10BXBG (2) I/O Interface Mode (DVCC3n = 2.5 V 0.2 V) In the table below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. 1. SCLK input mode (SIO0 to SIO6) Parameter SCLK period TxD data to SCLK rise of fall* TxD data hold after SCLK rise or fall* RxD data valid to SCLK rise or fall* RxD data hold after SCLK rise or fall* Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x 4x - 60 10x - 15 30 2x + 10 40.5 MHz Min 395 38 232 30 59 Max Max Unit ns ns ns ns ns * SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 2. SCLK output mode (SIO0 to SIO6) Parameter SCLK period (programmable) TxD data to SCLK rise TxD data hold after SCLK rise RxD data valid to SCLK rise RxD data hold after SCLK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 8x 4x - 10 4x - 10 60 0 40.5 MHz Min 197 88 88 60 0 Max Max Unit ns ns ns ns ns tSCY SCLK SCK Output Mode/ Active-High SCL Input Mode SCLK Active-Low SCK Input Mode OUTPUT DATA TxD tOSS 0 tSRD 1 tOHS 2 tHSR 1 VALID 2 VALID 3 VALID 3 INPUT DATA RxD 0 VALID TMP1962-427 2006-02-21 TMP1962C10BXBG 22.9 SBI Timing (1) I2C Mode In the table below, the letters x and T represent the fsys and T0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. Fast Mode Standard Mode fSYS = 8 MHz n = 4 fSYS = 32 MHz n = 4 Min 0 4.0 4.7 4.0 (Note 5) 4.7 0.0 250 4.0 (Note 5) 4.7 Parameter SCL clock frequency Hold time for START condition SCL clock low width (Input) (Note 1) Setup time for a repeated START condition Data hold time (Input) (Note 3, 4) Data setup time Setup time for STOP condition Bus free time between STOP and START conditions Symbol tSCL tHD:STA tLOW Equation Min 0 Unit kHz s s s s s ns s s Max Max 100 Min 0 0.6 1.3 0.6 0.6 0.0 100 0.6 1.3 Max 400 SCL clock high width (Output) (Note 2) tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Note 1: SCL clock low width (output) is calculated with (2 (n - 1) + 4) T. Standard mode: 6 sec Typ (fsys = 8 MHz, n = 4) Fast mode: 1.5 sec Typ (fsys = 32 MHz, n = 4) Note 2: SCL clock high width (output) is calculated with (2 (n - 1)) T. Standard mode: 4 sec Typ (fsys = 8MHz, n = 4) Fast mode: 1 sec Typ (fsys = 32 MHz, n = 4) Note 3: The output data hold time is equal to 12x. Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the fall edge of SCL. However, TMP1962C10BXBG SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. Note 5: Software-dependent tSCL tf SCL tHD;STA SDA S S: START condition Sr: Repeated START condition P: STOP condition Sr P tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF tLOW tr tHIGH Note 6: To operate the SBI in I2C Fast mode, the fysy frequency must be no less than 20 MHz. To operate the SBI in I2C Standard mode, the fsys frequency must be no less than 4 MHz. TMP1962-428 2006-02-21 TMP1962C10BXBG (2) Clock-Synchronous 8-Bit SIO Mode In the table below, the letters x and T represent the fsys and T0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. The electrical specifications below are for an SCK signal with a 50% duty cycle. 1. SCK Input Mode Parameter SCK period SO data to SCK rise SO data hold after SCK rise SI data valid to SCK rise SI data hold after SCK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - (6x + 30) (tSCY/2) + 4x 0 4x + 10 40.5 MHz Max Min 395 19 296 0 108 Max Unit ns ns ns ns ns 2. SCK Output Mode Parameter SCK period (programmable) SO data to SCK rise SO data hold after SCK rise SI data valid to SCK rise SI data hold after SCK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 2 *T (tSCY/2) - 20 (tSCY/2) - 20 2x + 30 0 n 32 MHz Max Min 1000 480 480 92 0 Max Unit ns ns ns ns ns tSCY SCLK tOSS OUTPUT DATA TxD 0 tSRD INPUT DATA TxD 0 VALID 1 VALID 1 tHSR 2 VALID 3 VALID tOHS 2 3 TMP1962-429 2006-02-21 TMP1962C10BXBG 22.10 Event Counter In the table below, the letter x represents the fsys cycle period. Equation Min 2X + 100 2X + 100 Parameter Clock low pulse width Clock high pulse width Symbol tVCKL tVCKH 40.5 MHz Min 149 149 Max Max Unit ns ns 22.11 Timer Capture In the table below, the letter x represents the fsys cycle period. Equation Min 2X + 100 2X + 100 Parameter Low pulse width High pulse width Symbol tCPL tCPH 40.5 MHz Min 149 149 Max Max Unit ns ns 22.12 General Interrupts In the table below, the letter x represents the fsys cycle period. Equation Min X + 100 X + 100 Parameter Low pulse width for INT0-INTA High pulse width for INT0-INTA Symbol tINTAL tINTAH 40.5 MHz Min 125 125 Max Max Unit ns ns 22.13 NMI and STOP Wake-up Interrupts Parameter Low pulse width for NMI and INT0-INT4 High pulse width for INT0-INT4 Symbol tINTBL tINTBH Equation Min 100 100 40.5 MHz Min 100 100 Max Max Unit ns ns 22.14 SCOUT Pin Parameter Clock high pulse width Clock low pulse width Symbol tSCH tSCL Equation Min 0.5T - 5 0.5T - 5 40.5 MHz Min 7.4 7.4 Max Max Unit ns ns Note: In the above table, the letter T represents the cycle period of the SCOUT output clock. tSCH SCOUT tSCL TMP1962-430 2006-02-21 TMP1962C10BXBG 22.15 Bus Request and Bus Acknowledge Signals BUSRQ (Note 1) BUSAK tBAA tABA AD0 to AD15 (Note 2) A0 to A23, RD , WR (Note 2) CS0 to CS3 , R / W , HWR ALE Parameter Bus float to BUSAK asserted Bus float after BUSAK negated Symbol tABA tBAA Equation Min 0 0 40.5 MHz Min 0 0 Max 80 80 Max 80 80 Unit ns ns Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP1962C10BXBG does not respond to BUSRQ until the wait state ends. Note 2: This broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. The pin holds the last logic value present at that pin before the bus is relinquished. This is dynamically accomplished through external load capacitances. The equipment manufacturer may maintain the bus at a predefined state by means of off-chip restores, but he or she should designconsidering the time (determined by the CR constant) it takes for a signal to reach a desired state. The on-chip, integrated programmable pull-up/pull-down resistors remain active, depending on internal signal states. TMP1962-431 2006-02-21 TMP1962C10BXBG 22.16 KWUP Input Pull-up Register Inactive Parameter Low pulse width for KEY0-D High pulse width for KEY0-D Symbol tkyTBL tkyTBH Equation Min 100 100 40.5 MHz Min 100 100 Max Max Unit ns ns Static Pull-up Parameter Low pulse width for KEY0-D Symbol tkyTBL Equation Min 100 40.5 MHz Min 100 Max Max Unit ns Dynamic Pull-up Parameter Low pulse width for KEY0-D Symbol tkyTBL Equation Min T2 + 100 40.5 MHz Min T2 + 100 Max Max Unit ns T2: Dynamic pull-up frequency 22.17 Dual Pulse Input Equation Min 8Y Y + 20 Y + 20 Parameter Dual input pulse period Dual input pulse setup Dual input pulse hold Symbol Tdcyc Tabs Tabh 40.5MHz Min 395 70 70 Max Max Unit ns ns ns Y: Sampling clock (fsys/2) A Tabs B Tabh Tdcyc 22.18 ADTRG Input Equation Min fsysy/2 + 20 fsysy/2 + 20 Parameter ADRG low level pulse width ADTRG high level pulse interval Symbol tadL Tadh 40.5 MHz Min 32.4 32.4 Max Max Unit ns ns TMP1962-432 2006-02-21 TMP1962C10BXBG 23. I/O Register Summary The internal I/O registers occupy 8-kbyte addresses from FFFFE000H through FFFFFFFFH. (Registers specified as Big-endian) 1. 2. 3. 4. 5. 6. 7. 8. 9. Ports Watchdog Timer (WDT) Real-Time Clock (RTC) 8-Bit Timer 16-Bit Timer I2CBUS/Serial I/O (SIO) UART/Serial I/O (SIO) 10-Bit A/D Converter (ADC) Key on Wake-up (KWUP) 10. 32-Bit Input Capture 11. 32-Bit Output Compare 12. Interrupt Controller (INTC) 13. DMA Controller (DMAC) 14. Chip Select (CS)/Wait Controller 15. Clock Generator (CG) 16. Flash Control 17. ROM Correction Table Organization Mnemonic Register Name Address 7 6 1 0 Bit Name Read/Write Reset Value Function Access R/W: Read/write. The user can read and write the register bit. R: W: Read only. Write only. W*: The user can read and write the register bit, but a read always returns a value of 1. TMP1962-433 2006-02-21 TMP1962C10BXBG Big-Endian [1] PORT Address FFFFF000H 1H P0CR 2H P1 3H P0 4H 5H 6H P1FC 7H P1CR 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF010H Mnemonic Address FFFFF020H 1H Mnemonic Address FFFFF030H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic 1H P2 2H 3H 4H 5H 6H P2FC 7H P2CR 8H P3FC 9H P3CR AH BH P3 CH DH P4 EH FH 2H P4FC 3H P4CR 4H 5H 6H 7H 8H 9H AH P6 BH P5 CH P6FC DH P6CR EH P5FC FH P5CR Address Mnemonic Address Mnemonic Address Mnemonic Address FFFFF070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFF040H PA 1H P9 2H P8 3H P7 4H PACR 5H 6H 7H 8H PAFC 9H AH BH CH DH EH FH FFFFF050H PE 1H PD 2H PC 3H PB 4H PECR 5H PDCR 6H PCCR 7H PBCR 8H PEFC 9H PDFC AH PCFC BH PBFC CH PEODE DH PDODE EH PCODE FH FFFFF060H PI 1H PH 2H PG 3H PF 4H PICR 5H PHCR 6H PGCR 7H PFCR 8H PIFC 9H PHFC AH PGFC BH PFFC CH DH EH FH PFODE Address Mnemonic Address FFFFF0D0H Mnemonic Address FFFFF0E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF0F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Mnemonic FFFFF0C0H PM 1H PL 2H PK 3H PJ 4H PMCR 5H PLCR 6H PKCR 7H PJCR 8H 9H PLFC AH PKFC BH PJFC CH DH EH FH 1H PP 2H PO 3H PN 4H 5H PPCR 6H POCR 7H PNCR 8H 9H AH BH PNFC CH DH EH FH PNODE CH (reserved) DH (reserved) EH (reserved) FH (reserved) TMP1962-434 2006-02-21 TMP1962C10BXBG Big-Endian [3] RTC Mnemonic Address Mnemonic Address FFFFF0B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [2] WDT Address FFFFF080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address Mnemonic FFFFF090H 1H 2H WDCR 3H WDMOD 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFF0A0H 1H 2H 3H RTCCR 4H 5H 6H 7H RTCREG 8H 9H AH BH CH DH EH FH [4] 8-Bit Timer Address FFFFF100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA1REG TA0REG TA01CR TA01RUN TAG0ST TAG0IM TA1FFCR TA01MOD TA3REG TA2REG TA23CR TA23RUN (reserved) (reserved) TA3FFCR TA23MOD Address FFFFF110H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA5REG TA4REG TA45CR TA45RUN TAG1ST TAG1IM TA5FFCR TA45MOD TA7REG TA6REG TA67CR TA67RUN (reserved) (reserved) TA7FFCR TA67MOD Address FFFFF120H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA9REG TA8REG TA89CR TA89RUN TAG2ST TAG2IM TA9FFCR TA89MOD TABREG TAAREG TAABCR TAABRUN (reserved) (reserved) TABFFCR TAABMOD Address FFFFF130H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic [5] 16-Bit Timer Address FFFFF140H 1H 2H 3H Mnemonic TB0FFCR TB0MOD TB0CR TB0RUN Address FFFFF150H 1H 2H 3H Mnemonic TB1FFCR TB1MOD TB1CR TB1RUN Address FFFFF160H 1H 2H 3H Mnemonic TB2FFCR TB2MOD TB2CR TB2RUN Address FFFFF170H 1H 2H 3H Mnemonic TB3FFCR TB3MOD TB3CR TB3RUN 4H (reserved) 5H (reserved) 6H 7H TB0ST 8H 9H AH BH CH DH EH FH TB0RG1H TB0RG1L TB0RG0H TB0RG0L TB0CP1H TB0CP1L TB0CP0H TB0CP0L 4H (reserved) 5H (reserved) 6H 7H TB1ST 8H 9H AH BH CH DH EH FH TB1RG1H TB1RG1L TB1RG0H TB1RG0L TB1CP1H TB1CP1L TB1CP0H TB1CP0L 4H (reserved) 5H (reserved) 6H 7H TB2ST 8H 9H AH BH CH DH EH FH TB2RG1H TB2RG1L TB2RG0H TB2RG0L TB2CP1H TB2CP1L TB2CP0H TB2CP0L 4H (reserved) 5H (reserved) 6H 7H TB3ST 8H 9H AH BH CH DH EH FH TB3RG1H TB3RG1L TB3RG0H TB3RG0L TB3CP1H TB3CP1L TB3CP0H TB3CP0L TMP1962-435 2006-02-21 TMP1962C10BXBG Big-Endian Address FFFFF180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF190H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF1F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF210H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF220H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFF230H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TMP1962-436 2006-02-21 TMP1962C10BXBG Big-Endian Address FFFFF240H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic [6] I2C/SIO Address Mnemonic [7] UART/SIO Address Mnemonic Address Mnemonic Address Mnemonic FFFFF250H SBICR2/SR 1H I2CAR 2H SBIDBR 3H SBICR1 4H SBICR0 5H 6H SBIBR1 7H SBIBR0 8H 9H AH BH CH DH EH FH FFFFF260H BR0CR 1H SC0MOD0 2H SC0CR 3H SC0BUF 4H 5H SC0MOD2 6H SC0MOD1 7H BR0ADD 8H BR1CR 9H SC1MOD0 AH SC1CR BH SC1BUF CH DH SC1MOD2 EH SC1MOD1 FH BR1ADD FFFFF270H BR2CR 1H SC2MOD0 2H SC2CR 3H SC2BUF 4H 5H SC2MOD2 6H SC2MOD1 7H BR2ADD 8H BR3CR 9H SC3MOD0 AH SC3CR BH SC3BUF CH DH SC3MOD2 EH SC3MOD1 FH BR3ADD FFFFF280H BR4CR 1H SC4MOD0 2H SC4CR 3H SC4BUF 4H 5H SC4MOD2 6H SC4MOD1 7H BR4ADD 8H BR5CR 9H SC5MOD0 AH SC5CR BH SC5BUF CH DH SC5MOD2 EH SC5MOD1 FH BR5ADD Address Mnemonic FFFFF290H BR6CR 1H SC6MOD0 2H SC6CR 3H SC6BUF 4H 5H SC6MOD2 6H SC6MOD1 7H BR6ADD 8H 9H AH BH CH DH EH FH TMP1962-437 2006-02-21 TMP1962C10BXBG Big-Endian [9] KWUP Address FFFFF310H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH [8] 10-Bit ADC Address FFFFF300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADREG19H ADREG19L ADREG08H ADREG08L ADREG3BH ADREG3BL ADREG2AH ADREG2AL ADREG5DH ADREG5DL ADREG4CH ADREG4CL ADREG7FH ADREG7FL ADREG6EH ADREG6EL Mnemonic Address FFFFF360H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Mnemonic KWUPST3 KWUPST2 KWUPST1 KWUPST0 KWUPST7 KWUPST6 KWUPST5 KWUPST4 KWUPSTB KWUPSTA KWUPST9 KWUPST8 Address Mnemonic FFFFF370H 1H 2H KWUPCNT 3H KWUPCLR 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH ADCOMREGH ADCOMREGL ADMOD3 (reserved) ADMOD1 ADMOD0 CH ADCLK DH EH FH ADMOD4 CH DH EH KWUPSTD FH KWUPSTC [10] 32-Bit Input Capture Address Mnemonic Address Mnemonic Address Mnemonic Address Mnemonic FFFFF400H 1H TBTCR 2H TBTRUN 3H TCCR 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH TBTCAP3 TBTCAP2 TBTCAP1 TBTCAP0 TCG1ST TCG1IM TCG0ST TCG0IM FFFFF410H 1H 2H 3H CAP0CR 4H 5H 6H 7H TCCAP0HH TCCAP0HL TCCAP0LH TCCAP0LL FFFFF420H 1H 2H 3H CAP2CR 4H 5H 6H 7H TCCAP2HH TCCAP2HL TCCAP2LH TCCAP2LL FFFFF430H 1H 2H 3H CAP4CR 4H 5H 6H 7H TCCAP4HH TCCAP4HL TCCAP4LH TCCAP4LL 8H 9H AH BH CAP1CR CH DH EH FH TCCAP1HH TCCAP1HL TCCAP1LH TCCAP1LL 8H 9H AH BH CAP3CR CH DH EH FH TCCAP3HH TCCAP3HL TCCAP3LH TCCAP3LL 8H 9H AH BH CAP5CR CH DH EH FH TCCAP5HH TCCAP5HL TCCAP5LH TCCAP5LL [11] 32-Bit Output Compare Address Mnemonic Address FFFFF450H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TCCMP0HH TCCMP0HL TCCMP0LH TCCMP0LL TCCMP1HH TCCMP1HL TCCMP1LH TCCMP1LL TCCMP2HH TCCMP2HL TCCMP2LH TCCMP2LL TCCMP3HH TCCMP3HL TCCMP3LH TCCMP3LL Address FFFFF460H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TCCMP4HH TCCMP4HL TCCMP4LH TCCMP4LL TCCMP5HH TCCMP5HL TCCMP5LH TCCMP5LL TCCMP6HH TCCMP6HL TCCMP6LH TCCMP6LL TCCMP7HH TCCMP7HL TCCMP7LH TCCMP7LL Address FFFFF470H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CMPCTL3 CMPCTL2 CMPCTL1 CMPCTL0 CMPCTL7 CMPCTL6 CMPCTL5 CMPCTL4 FFFFF440H 1H 2H 3H CAP6CR 4H 5H 6H 7H TCCAP6HH TCCAP6HL TCCAP6LH TCCAP6LL 8H 9H AH BH CAP7CR CH DH EH FH TCCAP7HH TCCAP7HL TCCAP7LH TCCAP7LL TMP1962-438 2006-02-21 TMP1962C10BXBG Big-Endian [12] INTC Address 1H 2H IMC0L 3H 4H IMC1H 5H 6H IMC1L 7H 8H IMC2H 9H AH IMC2L BH CH IMC3H DH EH IMC3L FH Mnemonic Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic FFFFE000H IMC0H FFFFE010H IMC4H 2H IMC4L 3H 4H IMC5H 5H 6H IMC5L 7H 8H IMC6H 9H AH IMC6L BH CH IMC7H DH EH IMC7L FH FFFFE020H IMC8H 2H IMC8L 3H 4H IMC9H 5H 6H IMC9L 7H 8H IMCAH 9H AH IMCAL BH CH IMCBH DH EH IMCBL FH FFFFE030H IMCCH 2H IMCCL 3H 4H IMCDH 5H 6H IMCDL 7H 8H IMCEH 9H AH IMCEL BH CH IMCFH DH EH IMCFL FH Address 1H Mnemonic Address FFFFE050H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE040H HIVR 2H LIVR 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFE060H INTCLR TMP1962-439 2006-02-21 TMP1962C10BXBG Big-Endian [13] DAMC Address 1H 2H CCR0L 3H 4H CSR0H 5H 6H CSR0L 7H 8H SAR0H 9H AH SAR0L BH CH DAR0H DH EH DAR0L FH Mnemonic Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic FFFFE200H CCR0H FFFFE210H BCR0H 2H BCR0L 3H 4H 5H 6H 7H 8H DTCR0H 9H AH DTCR0L BH CH DH EH FH FFFFE220H CCR1H 2H CCR1L 3H 4H CSR1H 5H 6H CSR1L 7H 8H SAR1H 9H AH SAR1L BH CH DAR1H DH EH DAR1L FH FFFFE230H BCR1H 2H BCR1L 3H 4H 5H 6H 7H 8H DTCR1H 9H AH DTCR1L BH CH DH EH FH Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic FFFFE240H CCR2H 2H CCR2L 3H 4H CSR2H 5H 6H CSR2L 7H 8H SAR2H 9H AH SAR2L BH CH DAR2H DH EH DAR2L FH FFFFE250H BCR2H 2H BCR2L 3H 4H 5H 6H 7H 8H DTCR2H 9H AH DTCR2L BH CH DH EH FH FFFFE260H CCR3H 2H CCR3L 3H 4H CSR3H 5H 6H CSR3L 7H 8H SAR3H 9H AH SAR3L BH CH DAR3H DH EH DAR3L FH FFFFE270H BCR3H 2H BCR3L 3H 4H 5H 6H 7H 8H DTCR3H 9H AH DTCR3L BH CH DH EH FH Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic FFFFE280H CCR4H 2H CCR4L 3H 4H CSR4H 5H 6H CSR4L 7H 8H SAR4H 9H AH SAR4L BH CH DAR4H DH EH DAR4L FH FFFFE290H BCR4H 2H BCR4L 3H 4H 5H 6H 7H 8H DTCR4H 9H AH DTCR4L BH CH DH EH FH FFFFE2A0H CCR5H 2H CCR5L 3H 4H CSR5H 5H 6H CSR5L 7H 8H SAR5H 9H AH SAR5L BH CH DAR5H DH EH DAR5L FH FFFFE2B0H BCR5H 2H BCR5L 3H 4H 5H 6H 7H 8H DTCR5H 9H AH DTCR5L BH CH DH EH FH TMP1962-440 2006-02-21 TMP1962C10BXBG Big-Endian Address 1H 2H CCR6L 3H 4H CSR6H 5H 6H CSR6L 7H 8H SAR6H 9H AH SAR6L BH CH DAR6H DH EH DAR6L FH Mnemonic Address 1H Mnemonic Address 1H Mnemonic Address 1H Mnemonic FFFFE2C0H CCR6H FFFFE2D0H BCR6H 2H BCR6L 3H 4H 5H 6H 7H 8H DTCR6H 9H AH DTCR6L BH CH DH EH FH FFFFE2E0H CCR7H 2H CCR7L 3H 4H CSR7H 5H 6H CSR7L 7H 8H SAR7H 9H AH SAR7L BH CH DAR7H DH EH DAR7L FH FFFFE2F0H BCR7H 2H BCR7L 3H 4H 5H 6H 7H 8H DTCR7H 9H AH DTCR7L BH CH DH EH FH Address 1H Mnemonic Address FFFFE310H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE320H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE330H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE300H DCRH 2H DCRL 3H 4H RSRH 5H 6H RSRL 7H 8H 9H AH BH CH DHRH DH EH DHRL FH Address FFFFE340H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE350H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE360H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFE370H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TMP1962-441 2006-02-21 TMP1962C10BXBG Big- Endian [14] CS/Wait Controller Address Mnemonic Address FFFFE410H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address Mnemonic Address FFFFE490H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE400H BMA0 1H 2H 3H 4H BMA1 5H 6H 7H 8H BMA2 9H AH BH CH BMA3 DH EH FH FFFFE480H B01CS 1H 2H 3H 4H B23CS 5H 6H 7H 8H BEXCS 9H AH BH CH DH EH FH [15] CG Address FFFFEE00H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic SYSCR3 SYSCR2 SYSCR1 SYSCR0 Address FFFFEE10H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic IMCGA3 IMCGA2 IMCGA1 IMCGA0 IMCGB3 IMCGB2 IMCGB1 IMCGB0 IMCGC3 IMCGC2 IMCGC1 IMCGC0 IMCGD3 IMCGD2 IMCGD1 IMCGD0 Address Mnemonic Address FFFFEE40H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFEE20H EICRCG 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [16] Flash Control Address Mnemonic Address Mnemonic [17] ROM Correction Address Mnemonic Address Mnemonic FFFFE510H SEQMOD 1H 2H 3H 4H SEQCNT 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFE520H FLCS 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFE540H ADDREG0 1H 2H 3H 4H ADDREG1 5H 6H 7H 8H ADDREG2 9H AH BH CH ADDREG3 DH EH FH FFFFE550H ADDREG4 1H 2H 3H 4H ADDREG5 5H 6H 7H 8H ADDREG6 9H AH BH CH ADDREG7 DH EH FH TMP1962-442 2006-02-21 TMP1962C10BXBG Little-Endian [1] PORT ADR Mnemonic 1H P1 2H P0CR 3H 4H P1CR 5H P1FC 6H 7H 8H 9H AH BH CH DH EH FH ADR FFFFF010H 1H Mnemonic ADR Mnemonic 1H P4FC 2H 3H 4H 5H 6H 7H 8H P5 9H P6 AH BH CH P5CR DH P5FC EH P6CR FH P6FC ADR FFFFF030H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFF000H P0 FFFFF020H P4CR 2H P2 3H 4H P2CR 5H P2FC 6H 7H 8H P3 9H AH P3CR BH P3FC CH DH EH P4 FH ADR Mnemonic 1H P8 2H P9 3H PA 4H 5H 6H 7H PACR 8H 9H AH BH PAFC CH DH EH FH ADR Mnemonic 1H PC 2H PD 3H PE 4H PBCR 5H PCCR 6H PDCR 7H PECR 8H PBFC 9H PCFC AH PDFC BH PEFC CH DH PCODE EH PDODE FH PEODE ADR Mnemonic 1H PG 2H PH 3H PI 4H PFCR 5H PGCR 6H PHCR 7H PICR 8H PFFC 9H PGFC AH PHFC BH PIFC CH PFODE DH EH FH ADR FFFFF070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFF040H P7 FFFFF050H PB FFFFF060H PF ADR Mnemonic 1H PK 2H PL 3H PM 4H PJCR 5H PKCR 6H PLCR 7H PMCR 8H PJFC 9H PKFC AH PLFC BH PMFC CH DH EH FH ADR Mnemonic 1H PO 2H PP 3H 4H PNCR 5H POCR 6H PPCR 7H 8H PNFC 9H POFC AH PPFC BH CH PNODE DH EH FH ADR FFFFF0E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF0F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Mnemonic FFFFF0C0H PJ FFFFF0D0H PN CH (reserved) DH (reserved) EH (reserved) FH (reserved) TMP1962-443 2006-02-21 TMP1962C10BXBG Little-Endian [3] RTC Mnemonic ADR Mnemonic ADR FFFFF0B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [2] WDT ADR FFFFF080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR Mnemonic FFFFF090H WDMOD 1H WDCR 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFF0A0H RTCCR 1H 2H 3H 4H RTCREG 5H 6H 7H 8H 9H AH BH CH DH EH FH [4] 8-Bit Timer ADR FFFFF100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA01RUN TA01CR TA0REG TA1REG TA01MOD TA1FFCR TAG0IM TAG0ST TA23RUN TA23CR TA2REG TA3REG TA23MOD TA3FFCR (reserved) (reserved) ADR FFFFF110H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA45RUN TA45CR TA4REG TA5REG TA45MOD TA5FFCR TAG1IM TAG1ST TA67RUN TA67CR TA6REG TA7REG TA67MOD TA7FFCR (reserved) (reserved) ADR FFFFF120H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TA89RUN TA89CR TA8REG TA9REG TA89MOD TA9FFCR TAG2IM TAG2ST TAABRUN TAABCR TAAREG TABREG TAABMOD TABFFCR (reserved) (reserved) ADR FFFFF130H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic [5] 16-Bit Timer ADR FFFFF140H 1H 2H 3H Mnemonic TB0RUN TB0CR TB0MOD TB0FFCR ADR FFFFF150H 1H 2H 3H Mnemonic TB1RUN TB1CR TB1MOD TB1FFCR ADR FFFFF160H 1H 2H 3H Mnemonic TB2RUN TB2CR TB2MOD TB2FFCR ADR FFFFF170H 1H 2H 3H Mnemonic TB3RUN TB3CR TB3MOD TB3FFCR 4H TB0ST 5H 6H (reserved) 7H (reserved) 8H 9H AH BH CH DH EH FH TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H 4H TB1ST 5H 6H (reserved) 7H (reserved) 8H 9H AH BH CH DH EH FH TB1RG0L TB1RG0H TB1RG1L TB1RG1H TB1CP0L TB1CP0H TB1CP1L TB1CP1H 4H TB2ST 5H 6H (reserved) 7H (reserved) 8H 9H AH BH CH DH EH FH TB2RG0L TB2RG0H TB2RG1L TB2RG1H TB2CP0L TB2CP0H TB2CP1L TB2CP1H 4H TB3ST 5H 6H (reserved) 7H (reserved) 8H 9H AH BH CH DH EH FH TB3RG0L TB3RG0H TB3RG1L TB3RG1H TB3CP0L TB3CP0H TB3CP1L TB3CP1H TMP1962-444 2006-02-21 TMP1962C10BXBG Little-Endian ADR FFFFF180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF190H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF1F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF210H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF220H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFF230H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TMP1962-445 2006-02-21 TMP1962C10BXBG Little-Endian ADR FFFFF240H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic [6] I2C/SIO ADR Mnemonic 1H SBIDBR 2H I2CAR 3H SBICR2/SR 4H SBIBR0 5H SBIBR1 6H 7H 8H 9H AH BH CH DH EH FH [7] UART/SIO ADR Mnemonic 1H SC0CR 2H SC0MOD0 3H BR0CR 4H BR0ADD 5H SC0MOD1 6H SC0MOD2 7H 8H SC1BUF 9H SC1CR AH SC1MOD0 BH BR1CR CH BR1ADD DH SC1MOD1 EH SC1MOD2 FH ADR Mnemonic 1H SC2CR 2H SC2MOD0 3H BR2CR 4H BR2ADD 5H SC2MOD1 6H SC2MOD2 7H 8H SC3BUF 9H SC3CR AH SC3MOD0 BH BR3CR CH BR3ADD DH SC3MOD1 EH SC3MOD2 FH ADR Mnemonic 1H SC4CR 2H SC4MOD0 3H BR4CR 4H BR4ADD 5H SC4MOD1 6H SC4MOD2 7H 8H SC5BUF 9H SC5CR AH SC5MOD0 BH BR5CR CH BR5ADD DH SC5MOD1 EH SC5MOD2 FH FFFFF250H SBICR1 FFFFF260H SC0BUF FFFFF270H SC2BUF FFFFF280H SC4BUF ADR Mnemonic 1H SC6CR 2H SC6MOD0 3H BR6CR 4H BR6ADD 5H SC6MOD1 6H SC6MOD2 7H 8H 9H AH BH CH DH EH FH FFFFF290H SC6BUF TMP1962-446 2006-02-21 TMP1962C10BXBG Little-Endian [9] KWUP ADR FFFFF310H 1H 2H 3H 4H ADCOMREGL 5H ADCOMREGH 6H 7H 8H 9H AH BH ADMOD0 ADMOD1 (reserved) ADMOD3 [8] 10-Bit ADC ADR FFFFF300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADREG08L ADREG08H ADREG19L ADREG19H ADREG2AL ADREG2AH ADREG3BL ADREG3BH ADREG4CL ADREG4CH ADREG5DL ADREG5DH ADREG6EL ADREG6EH ADREG7FL ADREG7FH Mnemonic ADR FFFFF360H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Mnemonic KWUPST0 KWUPST1 KWUPST2 KWUPST3 KWUPST4 KWUPST5 KWUPST6 KWUPST7 KWUPST8 KWUPST9 KWUPSTA KWUPSTB ADR Mnemonic FFFFF370H KWUPCLR 1H KWUPCNT 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH CH ADMOD4 DH EH FH ADCLK CH KWUPSTC DH KWUPSTD EH FH [10] 32-Bit Input Capture ADR Mnemonic ADR Mnemonic ADR Mnemonic ADR Mnemonic FFFFF 400H TCCR 1H TBTRUN 2H TBTCR 3H 4H 5H 6H 7H 8H 9H AH BH TBTCAP0 TBTCAP1 TBTCAP2 TBTCAP3 TCG0IM TCG0ST TCG1IM TCG1ST FFFFF410H CAP0CR 1H 2H 3H 4H 5H 6H 7H TCCAP0LL TCCAP0LH TCCAP0HL TCCAP0HH FFFFF420H CAP2CR 1H 2H 3H 4H 5H 6H 7H TCCAP2LL TCCAP2LH TCCAP2HL TCCAP2HH FFFFF430H CAP4CR 1H 2H 3H 4H 5H 6H 7H TCCAP4LL TCCAP4LH TCCAP4HL TCCAP4HH 8H CAP1CR 9H AH BH CH DH EH FH TCCAP1LL TCCAP1LH TCCAP1HL TCCAP1HH 8H CAP3CR 9H AH BH CH DH EH FH TCCAP3LL TCCAP3LH TCCAP3HL TCCAP3HH 8H CAP5CR 9H AH BH CH DH EH FH TCCAP5LL TCCAP5LH TCCAP5HL TCCAP5HH CH TCG2IM DH TCG2ST EH FH [11] 32-Bit Output Compare ADR Mnemonic ADR FFFFF450H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TCCMP0LL TCCMP0LH TCCMP0HL TCCMP0HH TCCMP1LL TCCMP1LH TCCMP1HL TCCMP1HH TCCMP2LL TCCMP2LH TCCMP2HL TCCMP2HH TCCMP3LL TCCMP3LH TCCMP3HL TCCMP3HH ADR FFFFF460H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TCCMP4LL TCCMP4LH TCCMP4HL TCCMP4HH TCCMP5LL TCCMP5LH TCCMP5HL TCCMP5HH TCCMP6LL TCCMP6LH TCCMP6HL TCCMP6HH TCCMP7LL TCCMP7LH TCCMP7HL TCCMP7HH ADR FFFFF470H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CMPCTL0 CMPCTL1 CMPCTL2 CMPCTL3 FFFFF 440H CAP6CR 1H 2H 3H 4H 5H 6H 7H TCCAP6LL TCCAP6LH TCCAP6HL TCCAP6HH 8H CAP7CR 9H AH BH CH DH EH FH TCCAP7LL TCCAP7LH TCCAP7HL TCCAP7HH Little-Endian TMP1962-447 2006-02-21 TMP1962C10BXBG [12] INTC ADR 1H 2H IMC0H 3H 4H IMC1L 5H 6H IMC1H 7H 8H IMC2L 9H AH IMC2H BH CH IMC3L DH EH IMC3H FH Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic FFFFE000H IMC0L FFFFE010H IMC4L 2H IMC4H 3H 4H IMC5L 5H 6H IMC5H 7H 8H IMC6L 9H AH IMC6H BH CH IMC7L DH EH IMC7H FH FFFFE020H IMC8L 2H IMC8H 3H 4H IMC9L 5H 6H IMC9H 7H 8H IMCAL 9H AH IMCAH BH CH IMCBL DH EH IMCBH FH FFFFE030H IMCCL 2H IMCCH 3H 4H IMCDL 5H 6H IMCDH 7H 8H IMCEL 9H AH IMCEH BH CH IMCFL DH EH IMCFH FH ADR 1H Mnemonic ADR FFFFE050H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE040H HIVR 2H LIVR 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFE060H INTCLR TMP1962-448 2006-02-21 TMP1962C10BXBG Little-Endian [13] DAMC ADR 1H 2H CCR0H 3H 4H CSR0L 5H 6H CSR0H 7H 8H SAR0L 9H AH SAR0H BH CH DAR0L DH EH DAR0H FH Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic FFFFE200H CCR0L FFFFE210H BCR0L 2H BCR0H 3H 4H 5H 6H 7H 8H DTCR0L 9H AH DTCR0H BH CH DH EH FH FFFFE220H CCR1L 2H CCR1H 3H 4H CSR1L 5H 6H CSR1H 7H 8H SAR1L 9H AH SAR1H BH CH DAR1L DH EH DAR1H FH FFFFE230H BCR1L 2H BCR1H 3H 4H 5H 6H 7H 8H DTCR1L 9H AH DTCR1H BH CH DH EH FH ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic FFFFE240H CCR2L 2H CCR2H 3H 4H CSR2L 5H 6H CSR2H 7H 8H SAR2L 9H AH SAR2H BH CH DAR2L DH EH DAR2H FH FFFFE250H BCR2L 2H BCR2H 3H 4H 5H 6H 7H 8H DTCR2L 9H AH DTCR1H BH CH DH EH FH FFFFE260H CCR3L 2H CCR3H 3H 4H CSR3L 5H 6H CSR3H 7H 8H SAR3L 9H AH SAR3H BH CH DAR3L DH EH DAR3H FH FFFFE270H BCR3L 2H BCR3H 3H 4H 5H 6H 7H 8H DTCR3L 9H AH DTCR3H BH CH DH EH FH ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic FFFFE280H CCR4L 2H CCR4H 3H 4H CSR4L 5H 6H CSR4H 7H 8H SAR4L 9H AH SAR4H BH CH DAR4L DH EH DAR4H FH FFFFE290H BCR4L 2H BCR4H 3H 4H 5H 6H 7H 8H DTCR4L 9H AH DTCR4H BH CH DH EH FH FFFFE2A0H CCR5L 2H CCR5H 3H 4H CSR5L 5H 6H CSR5H 7H 8H SAR5L 9H AH SAR5H BH CH DAR5L DH EH DAR5H FH FFFFE2B0H BCR5L 2H BCR5H 3H 4H 5H 6H 7H 8H DTCR5L 9H AH DTCR5H BH CH DH EH FH TMP1962-449 2006-02-21 TMP1962C10BXBG Little-Endian ADR 1H 2H CCR6H 3H 4H CSR6L 5H 6H CSR6H 7H 8H SAR6L 9H AH SAR6H BH CH DAR6L DH EH DAR6H FH Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic ADR 1H Mnemonic FFFFE2C0H CCR6L FFFFE2D0H BCR6L 2H BCR6H 3H 4H 5H 6H 7H 8H DTCR6L 9H AH DTCR6H BH CH DH EH FH FFFFE2E0H CCR7L 2H CCR7H 3H 4H CSR7L 5H 6H CSR7H 7H 8H SAR7L 9H AH SAR7H BH CH DAR7L DH EH DAR7H FH FFFFE2F0H BCR7L 2H BCR7H 3H 4H 5H 6H 7H 8H DTCR7L 9H AH DTCR7H BH CH DH EH FH ADR 1H Mnemonic ADR FFFFE310H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE320H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE330H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE300H DCRL 2H DCRH 3H 4H RSRL 5H 6H RSRH 7H 8H 9H AH BH CH DHRL DH EH DHRH FH ADR FFFFE340H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE350H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE360H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR FFFFE370H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TMP1962-450 2006-02-21 TMP1962C10BXBG Little-Endian [14] CS/Wait Controller ADR Mnemonic ADR FFFFE410H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADR Mnemonic ADR FFFFE490H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFE400H BMA0 1H 2H 3H 4H BMA1 5H 6H 7H 8H BMA2 9H AH BH CH BMA3 DH EH FH FFFFE480H B01CS 1H 2H 3H 4H B23CS 5H 6H 7H 8H BEXCS 9H AH BH CH DH EH FH [15] CG ADR FFFFEE00H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic SYSCR0 SYSCR1 SYSCR2 SYSCR3 ADR FFFFEE10H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic IMCGA0 IMCGA1 IMCGA2 IMCGA3 IMCGB0 IMCGB1 IMCGB2 IMCGB3 IMCGC0 IMCGC1 IMCGC2 IMCGC3 IMCGD0 IMCGD1 IMCGD2 IMCGD3 ADR Mnemonic ADR FFFFEE40H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FFFFEE20H EICRCG 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [16] Flash Control ADR Mnemonic ADR Mnemonic FFFFE510H SEQMOD 1H 2H 3H 4H SEQCNT 5H 6H 7H 8H 9H AH BH CH DH EH FH FFFFE520H FLCS 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [17] ROM Correction ADR Mnemonic ADR Mnemonic FFFFE540H ADDREG0 1H 2H 3H 4H ADDREG1 5H 6H 7H 8H ADDREG2 9H AH BH CH ADDREG3 DH EH FH FFFFE550H ADDREG4 1H 2H 3H 4H ADDREG5 5H 6H 7H 8H ADDREG6 9H AH BH CH ADDREG7 DH EH FH TMP1962-451 2006-02-21 TMP1962C10BXBG 24. I/O Port Equivalent-Circuit Diagrams * How to read circuit diagrams The circuit diagrams in this chapter are drawn using the same gate symbols as for the 74HCxx Series standard CMOS logic ICs. The signal named STOP has a unique function. This signal goes active-high if the CPU sets the HALT bit when the STBY[1:0] field in the SYSCR2 register is programmed to 01 (i.e., STOP mode) and the Drive Enable (DRVE) bit in the same register is cleared. If the DRVE bit is set, the STOP signal remains inactive (at logic 0). * The input protection circuit has a resistor in the range of several tens to several hundreds of ohms. P0 (D0-D7/AD0-AD7), P1 (D8-D15/AD8-AD15, A8-A15), P2 (A16-23, A0-7), P37,P44, P5 (A0-A7), P6 (A8-A15), PA, PB, PI7, PC1, PC4, PC7, PD2, PD5, PE1, PF2-PF7, PG, PH, PJ1-PJ4, PL, PM, PN1, PN3-PN7, PO, PP Vcc Output Data Output Enable STOP Input Data P-ch N-ch Input/Output Input Enable P30 ( RD ), P31 ( WR ), DCLK, PCST3-PCST0, SDAO/TPC, TDO Vcc Output Data Output STOP P32-P36, P40-P43 Vcc Output Data Output Enable STOP Input Data P-ch Vcc Programmable Pull-up Resistor Input/Output N-ch Input Enable TMP1962-452 2006-02-21 TMP1962C10BXBG P7 (AN0-AN7), P8 (AN8-AN15), P9 (AN16-AN23) Analog Input Channel Select Analog Input Input Input Data Input Enable PI0-PI6 ( ADTRG , INT1-INTA), PJ0 (INT0) VCC Output Data Output Enable STOP Input Data Schmitt-Trigger Input Enable P-ch N-ch Input/Output PC0, PC2, PC3,PC5, PC6, PD0, PD1, PD3, PD4, PD6, PE0, PE2, PN0, PN2 Vcc Output Data Open-Drain Output Enable Output Enable STOP Input Data Input/Output P-ch N-ch Input Enable PD7, PE3-PE7, PK Vcc Output Data P-ch Vcc Output Enable STOP Pull-up Resistor Control Input Data Schmitt-Trigger Input Enable N-ch Programmable Pull-up Resistor Input/Output TMP1962-453 2006-02-21 TMP1962C10BXBG PF0, PF1 Vcc Output Data Open-Drain Output Enable Output Enable STOP Input Data Schmitt-Trigger Input Enable Input/Output P-ch N-ch NMI , BW0-BW1, PLLOFF , RSTPUP Input Schmitt-Trigger RESET Vcc Reset Schmitt-Trigger WDTOUT Reset Enable Input DRESET , DBGE , SDI/ DINT , TCK, TMS, TDI Vcc Debug Reset Schmitt-Trigger Input TRST Input Schmitt-Trigger Test Reset TMP1962-454 2006-02-21 TMP1962C10BXBG X1, X2 Oscillator Circuit X2 High-Frequency Oscillator Enable X1 Clock VREFH, VREFL VREFON P-ch VREFH Ladder Resistors VREFL TMP1962-455 2006-02-21 TMP1962C10BXBG 25. Notations, Precautions and Restrictions 25.1 Notations and Terms (1) I/O register fields are often referred to as fgear: Clock selected by the SYSCR1.GEAR[1:0] bits The fsys cycle is referred to as a state. In addition, the clock selected by the SYSCR1.FPSEL bit and the prescaler clock source selected by the SYSCR0.PRCK[1:0] bits are referred to as fperiph and T0 respectively. 25.2 Precautions and Restrictions (1) Processor Revision Identifier The Process Revision Identifier (PRId) register in the TX19 core of the TMP1962C10B contains 0x0000_2CA1. (2) BW0-BW1 Pins The BW0 and BW1 pins must be connected to the DVCC2 pin to ensure that their signal levels do not fluctuate during chip operation. (3) Oscillator Warm-Up Counter If an external crystal is utilized, an interrupt signal programmed to bring the TMP1940CYAF out of STOP mode triggers the on-chip warm-up counter. The system clock is not supplied to the on-chip logic until the warm-up counter expires. (4) Programmable Pullup Resistors When port pins are configured as input ports, the integrated pull-up resistors can be enabled and disabled under software control. The pull-up resistors are not programmable when port pins are configured as output ports. The relevant port registers are programmed with the data resister. (5) External Bus Mastership The pin states while the bus is granted to an external device are described in Chapter 7, I/O Ports. (6) Watchdog Timer (WDT) Upon reset, the WDT is enabled. If the watchdog timer function is not required, it must be disabled after reset. When relevant pins are configured as bus arbitration signals, the I/O peripherals including the WDT can operate during external bus mastership. (7) A/D Converter (ADC) The ladder resistor network between the VREFH and VREFL pins can be disconnected under software control. This helps to reduce power dissipation, for example, in STOP mode. TMP1962-456 2006-02-21 TMP1962C10BXBG (8) Undefined Bits in I/O Registers Undefined I/O register bits are read as undefined states. Therefore, software must be coded without relying on the states of any undefined bits. (9) Electrostatic Discharge (ESD) Sensitivity The following shows ESD sensitivity. Protect the device from static damage during device development or production stage. For a detailed description on ESD, see General Safety Precautions and Usage Considerations. * TMP1962C10BXBG Specification Machine Model: MM Human Body Model: HBM Sensitivity 200 V 1500 V * TMP1962F10AXBG Specification Machine Model: MM Human Body Model: HBM Sensitivity 200 V 1200 V (10) Notations, Precautions and Restrictions Overflow Exception Problem: If an overflow exception caused a jump to the exception handler and the first instruction in that exception handler caused another exception, the EPC register should point to the address of the first instruction in the exception handler. However, the EPC register might contain the address that caused the overflow exception. * Problem-Causing Situation: When, with the instruction pipeline full, an overflow exception was taken at the following sequence of instructions and then the first instruction in the overflow exception handler causes another exception ADD, ADDI or SUB Delay slot Note: Toshiba's compiler uses no instructions that could cause an overflow. Therefore, this problem does not occur. <= # Instruction that causes an overflow Jump or branch instruction <= # Instruction with a delay slot Workaround: Don't place a jump or branch instruction immediately following an instruction that could cause an overflow (ADD, ADDI or SUB). TMP1962-457 2006-02-21 TMP1962C10BXBG LWL and LWR Instructions Problem: The LWL or LWR instruction might provide incorrect results. * Problem-Causing Situation #1: a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to that of the LWL or LWR instruction. b. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be executed consecutively.) c. The DMAC is programmed for data cache snooping. Once the load instruction is executed, the DMAC initiates a DMA transaction. After it has been serviced, the LWL or LWR instruction is executed. This problem occurs when all of these conditions are true. * Problem-Causing Situation #2: a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to that of the LWL or LWR instruction. b. The Doze or Halt bit in the Config register is set to 1 immediately before the load instruction. c. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be executed consecutively.) d. After the load instruction is executed, the processor is put in the STOP, SLEEP or IDLE mode. e. After an interrupt signaling brings the processor out of the STOP, SLEEP or IDLE mode, the LWL or LWR instruction is executed. Note: This applies to the case in which an interrupt signaling does not generate an interrupt upon exit from STOP or IDLE mode. In other words, either the IEc bit in the Status register is cleared (interrupts disabled), or if the IEc bit is set, the priority level of the incoming interrupt signaling is lower than the mask level programmed in the CMask field in the Status register. (Exit from STOP, SLEEP or IDLE mode can be accomplished even with such settings.) This problem occurs when all of these conditions are true. Workarounds: To use the LWL or LWR instruction, 1) Place a NOP between a load instruction and the LWL or LWR instruction, or 2) Disable the data cache snooping of the DMAC before the LWL or LWR instruction is executed. Also, do not put the processor in STOP, SLEEP or IDLE mode before the LWL or LWR instruction is executed. TMP1962-458 2006-02-21 TMP1962C10BXBG Overflow Exception When a DSU Probe Is Used Problem: It looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address (0xBFC0_0000). * Problem-Causing Situation: When an overflow exception occurs, with the processor connected to a DSU probe Note: Toshiba's compiler uses no instructions that could cause an overflow. Therefore, this problem does not occur. Workaround: Don't place a jump or branch instruction immediately following an instruction that could cause an overflow (ADD, ADDI or SUB). Malfunction of using BUSREQ signl in External Bus Access mode [Condition] In External Bus mode, using Auto WAIT insert function (as same as +N wait) Use External Bus request signal Function (BUSREQ). For each target product,Bus setting mode (Multiplex/ separate) ALE width(short/long) . Please refer to following table. (Exp: ALE Band =1.5CLK, Auto wait = 3 ) Internal Clock ALE Output (ALE=1.5CLK) RD Output ( Normal ) RD Output (abnormal ) Insert external Bus request (BUSREQ) When starting Bus cycle (S0) tRD spec not achieve because of 1 minus wait from original TMP1962-459 2006-02-21 |
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